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authorTony Tye <Tony.Tye@amd.com>2017-06-07 00:08:35 +0000
committerTony Tye <Tony.Tye@amd.com>2017-06-07 00:08:35 +0000
commitd9c251f46c83dcdbb1a949029a118771c594bb45 (patch)
treef6d8e4048d9fa948c735fe5b4bbce40ecedc3c70 /llvm/docs
parent708a21bd5faecb88a234b2bd6b598e4ec8a093b4 (diff)
downloadbcm5719-llvm-d9c251f46c83dcdbb1a949029a118771c594bb45.tar.gz
bcm5719-llvm-d9c251f46c83dcdbb1a949029a118771c594bb45.zip
Add documentation for various aspects of the AMDGPU backend.
Remove extra tabs. Builds sucessfully with Sphinx v1.5.5 Differential Revision: https://reviews.llvm.org/D33736 llvm-svn: 304848
Diffstat (limited to 'llvm/docs')
-rw-r--r--llvm/docs/AMDGPUUsage.rst2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index c8b4072661e..f6dcfc6b579 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -2549,7 +2549,7 @@ coherent) and so the L2 cache will coherent with the CPU and other agents.
always generate
(see comment for
previous fence).
- - Could be split into
+ - Could be split into
separate s_waitcnt
vmcnt(0) and
s_waitcnt
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