[AArch64][GlobalISel] Legalize narrow scalar ops again.

Since r279760, we've been marking as legal operations on narrow integer
types that have wider legal equivalents (for instance, G_ADD s8).
Compared to legalizing these operations, this reduced the amount of
extends/truncates required, but was always a weird legalization decision
made at selection time.

So far, we haven't been able to formalize it in a way that permits the
selector generated from SelectionDAG patterns to be sufficient.

Using a wide instruction (say, s64), when a narrower instruction exists
(s32) would introduce register class incompatibilities (when one narrow
generic instruction is selected to the wider variant, but another is
selected to the narrower variant).

It's also impractical to limit which narrow operations are matched for
which instruction, as restricting "narrow selection" to ranges of types
clashes with potentially incompatible instruction predicates.

Concerns were also raised regarding  MIPS64's sign-extended register
assumptions, as well as wrapping behavior.
See discussions in https://reviews.llvm.org/D26878.

Instead, legalize the operations.

Should we ever revert to selecting these narrow operations, we should
try to represent this more accurately: for instance, by separating
a "concrete" type on operations, and an "underlying" type on vregs, we
could move the "this narrow-looking op is really legal" decision to the
legalizer, and let the selector use the "underlying" vreg type only,
which would be guaranteed to map to a register class.

In any case, we eventually should mitigate:
- the performance impact by selecting no-op extract/truncates to COPYs
  (which we currently do), and the COPYs to register reuses (which we
  don't do yet).
- the compile-time impact by optimizing away extract/truncate sequences
  in the legalizer.

llvm-svn: 292827

1 files changed, 0 insertions, 35 deletions

diff --git a/llvm/docs/GlobalISel.rst b/llvm/docs/GlobalISel.rst
index fd247a534f6..176bd4edea3 100644
--- a/llvm/docs/GlobalISel.rst
+++ b/llvm/docs/GlobalISel.rst
@@ -358,41 +358,6 @@ existing patterns (as any pattern we can select is by definition legal).
 Expanding that to describe legalization actions is a much larger but
 potentially useful project.
 
-.. _milegalizer-scalar-narrow:
-
-Scalar narrow types
-^^^^^^^^^^^^^^^^^^^
-
-In the AArch64 port, we currently mark as legal operations on narrow integer
-types that have a legal equivalent in a wider type.
-
-For example, this:
-
-     %2(GPR,s8) = G_ADD %0, %1
-
-is selected to a 32-bit instruction:
-
-     %2(GPR32) = ADDWrr %0, %1
-
-This avoids unnecessarily legalizing operations that can be seen as legal:
-8-bit additions are supported, but happen to have a 32-bit result with the high
-24 bits undefined.
-
-``TODO``:
-This has implications regarding vreg classes (as narrow values can now be
-represented by wider vregs) and should be investigated further.
-
-``TODO``:
-In particular, s1 comparison results can be represented as wider values in
-different ways.
-SelectionDAG has the notion of BooleanContents, which allows targets to choose
-what true and false are when in a larger register:
-
-* ``ZeroOrOne`` --- if only 0 and 1 are valid bools, even in a larger register.
-* ``ZeroOrMinusOne`` --- if -1 is true (common for vector instructions,
-  where compares produce -1).
-* ``Undefined`` --- if only the low bit is relevant in determining truth.
-
 .. _milegalizer-non-power-of-2:
 
 Non-power of 2 types