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| author | Tony Tye <Tony.Tye@amd.com> | 2017-06-07 00:46:08 +0000 |
|---|---|---|
| committer | Tony Tye <Tony.Tye@amd.com> | 2017-06-07 00:46:08 +0000 |
| commit | 3b34061367c8a81b157c652fb8972884c3acc8b8 (patch) | |
| tree | 053b9587e0759a1de0ac7fa0d8745aba7888df84 /llvm/docs | |
| parent | 17c59472e8598ff369ef1accb6a05ebe86d79d69 (diff) | |
| download | bcm5719-llvm-3b34061367c8a81b157c652fb8972884c3acc8b8.tar.gz bcm5719-llvm-3b34061367c8a81b157c652fb8972884c3acc8b8.zip | |
Try to work around possible bugs in version of Shpinx on buildserver.
Builds sucessfully with Sphinx v1.5.5
Differential Revision: https://reviews.llvm.org/D33736
llvm-svn: 304853
Diffstat (limited to 'llvm/docs')
| -rw-r--r-- | llvm/docs/AMDGPUUsage.rst | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst index f6dcfc6b579..ae7fbe2e89f 100644 --- a/llvm/docs/AMDGPUUsage.rst +++ b/llvm/docs/AMDGPUUsage.rst @@ -1468,9 +1468,9 @@ CP microcode requires the Kernel descritor to be allocated on 64 byte alignment. .. table:: compute_pgm_rsrc1 for GFX6-GFX9 :name: amdgpu-amdhsa-compute_pgm_rsrc1_t-gfx6-gfx9-table - ======= ======= =============================== =========================== + ======= ======= =============================== =========================================================================== Bits Size Field Name Description - ======= ======= =============================== =========================== + ======= ======= =============================== =========================================================================== 5:0 6 bits granulated_workitem_vgpr_count Number of vector registers used by each work-item, granularity is device @@ -1626,16 +1626,16 @@ CP microcode requires the Kernel descritor to be allocated on 64 byte alignment. ``COMPUTE_PGM_RSRC1.CDBG_USER``. 31:26 6 bits Reserved. Must be 0. 32 **Total size 4 bytes** - ======= =================================================================== + ======= =================================================================================================================== .. .. table:: compute_pgm_rsrc2 for GFX6-GFX9 :name: amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table - ======= ======= =============================== =========================== + ======= ======= =============================== =========================================================================== Bits Size Field Name Description - ======= ======= =============================== =========================== + ======= ======= =============================== =========================================================================== 0 1 bit enable_sgpr_private_segment Enable the setup of the _wave_offset SGPR wave scratch offset system register (see @@ -1783,7 +1783,7 @@ CP microcode requires the Kernel descritor to be allocated on 64 byte alignment. only) 31 1 bit Reserved. Must be 0. 32 **Total size 4 bytes.** - ======= =================================================================== + ======= =================================================================================================================== .. |
