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| author | Nikolai Bozhenov <nikolai.bozhenov@intel.com> | 2017-01-12 19:54:27 +0000 |
|---|---|---|
| committer | Nikolai Bozhenov <nikolai.bozhenov@intel.com> | 2017-01-12 19:54:27 +0000 |
| commit | f02ac0eeb2beadef8d5fe5e480dbbf64150b214a (patch) | |
| tree | 102f0122821599c573e0ae25e379125b49b4864c /llvm/docs/conf.py | |
| parent | 6503f24da853ed3c127b4b2704cd58538cbcf974 (diff) | |
| download | bcm5719-llvm-f02ac0eeb2beadef8d5fe5e480dbbf64150b214a.tar.gz bcm5719-llvm-f02ac0eeb2beadef8d5fe5e480dbbf64150b214a.zip | |
[X86] Replace AND+IMM64 with SRL/SHL
Emit SHRQ/SHLQ instead of ANDQ with a 64 bit constant mask if the result
is unused and the mask has only higher/lower bits set. For example, with
this patch LLVM emits
shrq $41, %rdi
je
instead of
movabsq $0xFFFFFE0000000000, %rcx
testq %rcx, %rdi
je
This reduces number of instructions, code size and register pressure.
The transformation is applied only for cases where the mask cannot be
encoded as an immediate value within TESTQ instruction.
Differential Revision: https://reviews.llvm.org/D28198
llvm-svn: 291806
Diffstat (limited to 'llvm/docs/conf.py')
0 files changed, 0 insertions, 0 deletions
