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| author | Dan Gohman <gohman@apple.com> | 2009-01-28 21:36:46 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2009-01-28 21:36:46 +0000 |
| commit | 511d5ece2b845e265c361a1212b0f8c355413c4a (patch) | |
| tree | b80c2a4a63cb64578fe98855039b63f68cc3ff1c /llvm/docs/WritingAnLLVMBackend.html | |
| parent | f52ac415665a983709eeb9dc69b96a5ecbba5a8b (diff) | |
| download | bcm5719-llvm-511d5ece2b845e265c361a1212b0f8c355413c4a.tar.gz bcm5719-llvm-511d5ece2b845e265c361a1212b0f8c355413c4a.zip | |
SDOperand has been renamed to SDValue. SDNode::Val is now
accessed via SDNode::getNode.
llvm-svn: 63240
Diffstat (limited to 'llvm/docs/WritingAnLLVMBackend.html')
| -rw-r--r-- | llvm/docs/WritingAnLLVMBackend.html | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/llvm/docs/WritingAnLLVMBackend.html b/llvm/docs/WritingAnLLVMBackend.html index 0f38955f4ee..08da132028d 100644 --- a/llvm/docs/WritingAnLLVMBackend.html +++ b/llvm/docs/WritingAnLLVMBackend.html @@ -1349,9 +1349,9 @@ ISD::STORE opcode.</p> </div> <div class="doc_code"> -<pre>SDNode *SelectCode(SDOperand N) { +<pre>SDNode *SelectCode(SDValue N) { ... - MVT::ValueType NVT = N.Val->getValueType(0); + MVT::ValueType NVT = N.getNode()->getValueType(0); switch (N.getOpcode()) { case ISD::STORE: { switch (NVT) { @@ -1372,21 +1372,21 @@ instruction. </p> </div> <div class="doc_code"> -<pre>SDNode *Select_ISD_STORE(const SDOperand &N) { - SDOperand Chain = N.getOperand(0); - if (Predicate_store(N.Val)) { - SDOperand N1 = N.getOperand(1); - SDOperand N2 = N.getOperand(2); - SDOperand CPTmp0; - SDOperand CPTmp1; +<pre>SDNode *Select_ISD_STORE(const SDValue &N) { + SDValue Chain = N.getOperand(0); + if (Predicate_store(N.getNode())) { + SDValue N1 = N.getOperand(1); + SDValue N2 = N.getOperand(2); + SDValue CPTmp0; + SDValue CPTmp1; // Pattern: (st:void IntRegs:i32:$src, // ADDRrr:i32:$addr)<<P:Predicate_store>> // Emits: (STrr:void ADDRrr:i32:$addr, IntRegs:i32:$src) // Pattern complexity = 13 cost = 1 size = 0 if (SelectADDRrr(N, N2, CPTmp0, CPTmp1) && - N1.Val->getValueType(0) == MVT::i32 && - N2.Val->getValueType(0) == MVT::i32) { + N1.getNode()->getValueType(0) == MVT::i32 && + N2.getNode()->getValueType(0) == MVT::i32) { return Emit_22(N, SP::STrr, CPTmp0, CPTmp1); } ... @@ -1520,8 +1520,8 @@ code, an FP_TO_SINT opcode will call the <tt>LowerFP_TO_SINT</tt> method:</p> </div> <div class="doc_code"> -<pre>SDOperand SparcTargetLowering::LowerOperation( - SDOperand Op, SelectionDAG &DAG) { +<pre>SDValue SparcTargetLowering::LowerOperation( + SDValue Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); ... @@ -1535,7 +1535,7 @@ register to convert the floating-point value to an integer.</p> </div> <div class="doc_code"> -<pre>static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { +<pre>static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { assert(Op.getValueType() == MVT::i32); Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0)); return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); |

