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authorNicolai Haehnle <nhaehnle@gmail.com>2018-03-14 11:00:43 +0000
committerNicolai Haehnle <nhaehnle@gmail.com>2018-03-14 11:00:43 +0000
commit77841b159abd5767fec6d26223420ec6d99c617d (patch)
tree166430d22bdeccac0d5913dad959448ade4a830e /llvm/docs/TableGen
parentef60a26817c68539125242b1b3cbf91fb850b657 (diff)
downloadbcm5719-llvm-77841b159abd5767fec6d26223420ec6d99c617d.tar.gz
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TableGen: Type-check BinOps
Additionally, allow more than two operands to !con, !add, !and, !or in the same way as is already allowed for !listconcat and !strconcat. Change-Id: I9659411f554201b90cd8ed7c7e004d381a66fa93 Differential revision: https://reviews.llvm.org/D44112 llvm-svn: 327494
Diffstat (limited to 'llvm/docs/TableGen')
-rw-r--r--llvm/docs/TableGen/LangIntro.rst8
1 files changed, 6 insertions, 2 deletions
diff --git a/llvm/docs/TableGen/LangIntro.rst b/llvm/docs/TableGen/LangIntro.rst
index 1f9b44586d9..75bce2b5216 100644
--- a/llvm/docs/TableGen/LangIntro.rst
+++ b/llvm/docs/TableGen/LangIntro.rst
@@ -267,8 +267,12 @@ supported include:
on string, int and bit objects. Use !cast<string> to compare other types of
objects.
-``!shl(a,b)`` ``!srl(a,b)`` ``!sra(a,b)`` ``!add(a,b)`` ``!and(a,b)``
- The usual binary and arithmetic operators.
+``!shl(a,b)`` ``!srl(a,b)`` ``!sra(a,b)``
+ The usual shift operators. Operations are on 64-bit integers, the result
+ is undefined for shift counts outside [0, 63].
+
+``!add(a,b,...)`` ``!and(a,b,...)`` ``!or(a,b,...)``
+ The usual arithmetic and binary operators.
Note that all of the values have rules specifying how they convert to values
for different types. These rules allow you to assign a value like "``7``"
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