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| author | Kerry McLaughlin <kerry.mclaughlin@arm.com> | 2019-09-02 16:12:31 +0000 |
|---|---|---|
| committer | Kerry McLaughlin <kerry.mclaughlin@arm.com> | 2019-09-02 16:12:31 +0000 |
| commit | da4ef9b4c86d0002f57f6cb9c4bfb6c435f2bef6 (patch) | |
| tree | 5d290f4bdefb8a88352b85fcd47f633853eb6faa /llvm/docs/LangRef.rst | |
| parent | 4fa267bcbb6fb7bfb963a8b8bae3c0ac60fec1ce (diff) | |
| download | bcm5719-llvm-da4ef9b4c86d0002f57f6cb9c4bfb6c435f2bef6.tar.gz bcm5719-llvm-da4ef9b4c86d0002f57f6cb9c4bfb6c435f2bef6.zip | |
[SVE][Inline-Asm] Support for SVE asm operands
Summary:
Adds the following inline asm constraints for SVE:
- w: SVE vector register with full range, Z0 to Z31
- x: Restricted to registers Z0 to Z15 inclusive.
- y: Restricted to registers Z0 to Z7 inclusive.
This change also adds the "z" modifier to interpret a register as an SVE register.
Not all of the bitconvert patterns added by this patch are used, but they have been included here for completeness.
Reviewers: t.p.northover, sdesmalen, rovka, momchil.velikov, rengolin, cameron.mcinally, greened
Reviewed By: sdesmalen
Subscribers: javed.absar, tschuett, rkruppe, psnobl, cfe-commits, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D66302
llvm-svn: 370673
Diffstat (limited to 'llvm/docs/LangRef.rst')
| -rw-r--r-- | llvm/docs/LangRef.rst | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst index f35ceb8518f..ff456102664 100644 --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -3811,8 +3811,9 @@ AArch64: offsets). (However, LLVM currently does this for the ``m`` constraint as well.) - ``r``: A 32 or 64-bit integer register (W* or X*). -- ``w``: A 32, 64, or 128-bit floating-point/SIMD register. -- ``x``: A lower 128-bit floating-point/SIMD register (``V0`` to ``V15``). +- ``w``: A 32, 64, or 128-bit floating-point, SIMD or SVE vector register. +- ``x``: Like w, but restricted to registers 0 to 15 inclusive. +- ``y``: Like w, but restricted to SVE vector registers Z0 to Z7 inclusive. AMDGPU: |
