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author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2016-06-09 15:19:16 +0000 |
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committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2016-06-09 15:19:16 +0000 |
commit | 79564611d9f982935952d3b62ef5918122fa5919 (patch) | |
tree | c8b75b762e2ef64436929959440a409c88d410bd /llvm/docs/LangRef.rst | |
parent | db0168d1d669e0a21f889a67a86e883ec60fd701 (diff) | |
download | bcm5719-llvm-79564611d9f982935952d3b62ef5918122fa5919.tar.gz bcm5719-llvm-79564611d9f982935952d3b62ef5918122fa5919.zip |
[SystemZ] Enable long displacement constraints for inline ASM operands
This enables use of the 'S' constraint for inline ASM operands on
SystemZ, which allows for a memory reference with a signed 20-bit
immediate displacement. This patch includes corresponding documentation
and test case updates.
I've changed the 'T' constraint to match the new behavior for 'S', as
'T' also uses a long displacement (though index constraints are still
not implemented). I also changed 'm' to match the behavior for 'S' as
this will allow for a wider range of displacements for 'm', though
correct me if that's not the right decision.
Author: colpell
Differential Revision: http://reviews.llvm.org/D21097
llvm-svn: 272266
Diffstat (limited to 'llvm/docs/LangRef.rst')
-rw-r--r-- | llvm/docs/LangRef.rst | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst index d9de43e3e4d..1b0d0cf5e6d 100644 --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -3590,8 +3590,10 @@ SystemZ: - ``K``: An immediate signed 16-bit integer. - ``L``: An immediate signed 20-bit integer. - ``M``: An immediate integer 0x7fffffff. -- ``Q``, ``R``, ``S``, ``T``: A memory address operand, treated the same as - ``m``, at the moment. +- ``Q``, ``R``: A memory address operand with a base address and a 12-bit + immediate unsigned displacement. +- ``S``, ``T``: A memory address operand with a base address and a 20-bit + immediate signed displacement. - ``r`` or ``d``: A 32, 64, or 128-bit integer register. - ``a``: A 32, 64, or 128-bit integer address register (excludes R0, which in an address context evaluates as zero). |