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| author | Reid Spencer <rspencer@reidspencer.com> | 2007-07-20 20:03:33 +0000 |
|---|---|---|
| committer | Reid Spencer <rspencer@reidspencer.com> | 2007-07-20 20:03:33 +0000 |
| commit | 65a72e37759b8187980c85dc27b42c201f3761fc (patch) | |
| tree | 1e14ee0e704a5fb1e822bea6449b85e7f65587e0 /llvm/docs/LangRef.html | |
| parent | 5b2cb0f88cc8e2a6a7dfe5ec9e0f4cec0016e93a (diff) | |
| download | bcm5719-llvm-65a72e37759b8187980c85dc27b42c201f3761fc.tar.gz bcm5719-llvm-65a72e37759b8187980c85dc27b42c201f3761fc.zip | |
Silly HTML
llvm-svn: 40117
Diffstat (limited to 'llvm/docs/LangRef.html')
| -rw-r--r-- | llvm/docs/LangRef.html | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/docs/LangRef.html b/llvm/docs/LangRef.html index fa7fefafc47..a45aba896b3 100644 --- a/llvm/docs/LangRef.html +++ b/llvm/docs/LangRef.html @@ -5078,13 +5078,13 @@ declare void @llvm.memory.barrier( i1 <ll>, i1 <ls>, i1 <sl>, <p> The <tt>llvm.memory.barrier</tt> intrinsic requires four boolean arguments. Each argument enables a specific barrier as listed below. +</p> <ul> <li><tt>ll</tt>: load-load barrier</li> <li><tt>ls</tt>: load-store barrier</li> <li><tt>sl</tt>: store-load barrier</li> <li><tt>ss</tt>: store-store barrier</li> </ul> -</p> <h5>Semantics:</h5> <p> This intrinsic causes the system to enforce some ordering constraints upon @@ -5094,6 +5094,7 @@ declare void @llvm.memory.barrier( i1 <ll>, i1 <ls>, i1 <sl>, (f.ex. load-load, or store-load), all of the first operations preceding the barrier will complete before any of the second operations succeeding the barrier begin. Specifically the semantics for each pairing is as follows: +</p> <ul> <li><tt>ll</tt>: All loads before the barrier must complete before any load after the barrier begins.</li> @@ -5104,6 +5105,7 @@ declare void @llvm.memory.barrier( i1 <ll>, i1 <ls>, i1 <sl>, <li><tt>sl</tt>: All stores before the barrier must complete before any load after the barrier begins.</li> </ul> +<p> These semantics are applied with a logical "and" behavior when more than one is enabled in a single memory barrier intrinsic. </p> |
