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| author | Craig Topper <craig.topper@intel.com> | 2018-11-30 08:32:01 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-11-30 08:32:01 +0000 |
| commit | 6e4b266a0d0aae8084908be011d1d696fc35c89d (patch) | |
| tree | 96b44f23e35ac5237cd079213d0ad12889ec9c8f /llvm/docs/HowToSetUpLLVMStyleRTTI.rst | |
| parent | ecc7dcb879c3917f8e2092969511aa5776dcb398 (diff) | |
| download | bcm5719-llvm-6e4b266a0d0aae8084908be011d1d696fc35c89d.tar.gz bcm5719-llvm-6e4b266a0d0aae8084908be011d1d696fc35c89d.zip | |
[X86] Change the pre-sse4.1 code in the v16i8 MULHU lowering to be what we get after DAG combine cleans it up.
Previously we emitted a punpcklbw/punpckhbw to move the byte elements into the upper half of 16 bit elements then shifted right by 8 to zero the upper bits. After DAG combine we end up with punpcklbw/punpckhbw into the lower bits with zeros in the uppers bits and no shifts. So just emit that directly.
llvm-svn: 347966
Diffstat (limited to 'llvm/docs/HowToSetUpLLVMStyleRTTI.rst')
0 files changed, 0 insertions, 0 deletions
