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| author | Craig Topper <craig.topper@intel.com> | 2018-05-10 05:43:43 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-05-10 05:43:43 +0000 |
| commit | 74ac0eda685e2a2e286b02cb679b68fd57c636b2 (patch) | |
| tree | 5efd2c185c0eca69871b8fc6bcab63a58495780a /llvm/docs/CommandGuide/llvm-lib.rst | |
| parent | ae56a957afd5e4e51a7e9374ef91a8e143b6e6c0 (diff) | |
| download | bcm5719-llvm-74ac0eda685e2a2e286b02cb679b68fd57c636b2.tar.gz bcm5719-llvm-74ac0eda685e2a2e286b02cb679b68fd57c636b2.zip | |
[X86] Change the implementation of scalar masked load/store intrinsics to not use a 512-bit intermediate vector.
This is unnecessary for AVX512VL supporting CPUs like SKX. We can just emit a 128-bit masked load/store here no matter what. The backend will widen it to 512-bits on KNL CPUs.
Fixes the frontend portion of PR37386. Need to fix the backend to optimize the new sequences well.
llvm-svn: 331958
Diffstat (limited to 'llvm/docs/CommandGuide/llvm-lib.rst')
0 files changed, 0 insertions, 0 deletions
