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authorDmitri Gribenko <gribozavr@gmail.com>2012-12-01 12:13:48 +0000
committerDmitri Gribenko <gribozavr@gmail.com>2012-12-01 12:13:48 +0000
commit7174c5a074f4361fe53ee27e066b7fbc5cca82e2 (patch)
treefa394e2872429fb3b7f4ba5afc288e89627de701 /llvm/docs/CodeGenerator.rst
parent5586bdfd2a371a6af8a4481f4e1c8a53bfe0197c (diff)
downloadbcm5719-llvm-7174c5a074f4361fe53ee27e066b7fbc5cca82e2.tar.gz
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Documentation: convert WritingAnLLVMBackend.html to reST
llvm-svn: 169087
Diffstat (limited to 'llvm/docs/CodeGenerator.rst')
-rw-r--r--llvm/docs/CodeGenerator.rst4
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/docs/CodeGenerator.rst b/llvm/docs/CodeGenerator.rst
index e2bbdb548cc..cafa93e46a5 100644
--- a/llvm/docs/CodeGenerator.rst
+++ b/llvm/docs/CodeGenerator.rst
@@ -250,6 +250,8 @@ operations. Among other things, this class indicates:
* various high-level characteristics, like whether it is profitable to turn
division by a constant into a multiplication sequence.
+.. _TargetRegisterInfo:
+
The ``TargetRegisterInfo`` class
--------------------------------
@@ -771,6 +773,8 @@ value of type i1, i8, i16, or i64 would be illegal, as would a DAG that uses a
SREM or UREM operation. The `legalize types`_ and `legalize operations`_ phases
are responsible for turning an illegal DAG into a legal DAG.
+.. _SelectionDAG-Process:
+
SelectionDAG Instruction Selection Process
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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