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| author | Jakub Staszak <kubastaszak@gmail.com> | 2012-04-15 20:13:47 +0000 |
|---|---|---|
| committer | Jakub Staszak <kubastaszak@gmail.com> | 2012-04-15 20:13:47 +0000 |
| commit | 89f1d0a5a456a65b9e583e0849c0351f6174cbb2 (patch) | |
| tree | befc003c766495678814f74e713d6a9e1a63d169 /llvm/docs/CodeGenerator.html | |
| parent | 42bcd04ee3e55c694f10db115a769fd6295c067a (diff) | |
| download | bcm5719-llvm-89f1d0a5a456a65b9e583e0849c0351f6174cbb2.tar.gz bcm5719-llvm-89f1d0a5a456a65b9e583e0849c0351f6174cbb2.zip | |
Fix filename and register numbers.
llvm-svn: 154771
Diffstat (limited to 'llvm/docs/CodeGenerator.html')
| -rw-r--r-- | llvm/docs/CodeGenerator.html | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/docs/CodeGenerator.html b/llvm/docs/CodeGenerator.html index 77bd625a4e5..313874e40a2 100644 --- a/llvm/docs/CodeGenerator.html +++ b/llvm/docs/CodeGenerator.html @@ -1617,9 +1617,9 @@ def : Pat<(i32 imm:$imm), range from 1 to 1023. To see how this numbering is defined for a particular architecture, you can read the <tt>GenRegisterNames.inc</tt> file for that architecture. For instance, by - inspecting <tt>lib/Target/X86/X86GenRegisterNames.inc</tt> we see that the - 32-bit register <tt>EAX</tt> is denoted by 15, and the MMX register - <tt>MM0</tt> is mapped to 48.</p> + inspecting <tt>lib/Target/X86/X86GenRegisterInfo.inc</tt> we see that the + 32-bit register <tt>EAX</tt> is denoted by 43, and the MMX register + <tt>MM0</tt> is mapped to 65.</p> <p>Some architectures contain registers that share the same physical location. A notable example is the X86 platform. For instance, in the X86 architecture, |
