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| author | Simon Dardis <simon.dardis@imgtec.com> | 2016-12-13 11:07:51 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@imgtec.com> | 2016-12-13 11:07:51 +0000 |
| commit | 43b5ce492d4480c6bca08351e36f47da8413776c (patch) | |
| tree | bb367c86f15aebffca94018cece1a7a40c575bf9 /llvm/docs/BitCodeFormat.rst | |
| parent | 2d9adbf5244292537b30946570ac73ff8b2219b8 (diff) | |
| download | bcm5719-llvm-43b5ce492d4480c6bca08351e36f47da8413776c.tar.gz bcm5719-llvm-43b5ce492d4480c6bca08351e36f47da8413776c.zip | |
[mips] Fix compact branch hazard detection
In certain cases it is possible that transient instructions such as
%reg = IMPLICIT_DEF as a single instruction in a basic block to reach
the MipsHazardSchedule pass. This patch teaches MipsHazardSchedule to
properly look through such cases.
Reviewers: vkalintiris, zoran.jovanovic
Differential Revision: https://reviews.llvm.org/D27209
llvm-svn: 289529
Diffstat (limited to 'llvm/docs/BitCodeFormat.rst')
0 files changed, 0 insertions, 0 deletions
