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| author | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2018-12-17 17:38:11 +0000 |
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| committer | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2018-12-17 17:38:11 +0000 |
| commit | 47eb63684d22c12b9defb99c394dbd10e26fefff (patch) | |
| tree | f497778b8180320c30d0dda8125e049f5a7d1916 /llvm/docs/AMDGPUUsage.rst | |
| parent | f700c8b25378acf912982788340f4ab10d8a15ec (diff) | |
| download | bcm5719-llvm-47eb63684d22c12b9defb99c394dbd10e26fefff.tar.gz bcm5719-llvm-47eb63684d22c12b9defb99c394dbd10e26fefff.zip | |
[AMDGPU][MC][DOC] Updated AMD GPU assembler description
Stage 2: added detailed description of operands
See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572
llvm-svn: 349368
Diffstat (limited to 'llvm/docs/AMDGPUUsage.rst')
| -rw-r--r-- | llvm/docs/AMDGPUUsage.rst | 37 |
1 files changed, 16 insertions, 21 deletions
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst index 5ca49752476..c60d60af5a8 100644 --- a/llvm/docs/AMDGPUUsage.rst +++ b/llvm/docs/AMDGPUUsage.rst @@ -4558,21 +4558,26 @@ Instructions .. toctree:: :hidden: - AMDGPUAsmGFX7 - AMDGPUAsmGFX8 - AMDGPUAsmGFX9 + AMDGPU/AMDGPUAsmGFX7 + AMDGPU/AMDGPUAsmGFX8 + AMDGPU/AMDGPUAsmGFX9 + AMDGPUModifierSyntax AMDGPUOperandSyntax + AMDGPUInstructionSyntax + AMDGPUInstructionNotation -An instruction has the following syntax: +An instruction has the following :doc:`syntax<AMDGPUInstructionSyntax>`: - *<opcode> <operand0>, <operand1>,... <modifier0> <modifier1>...* + ``<``\ *opcode*\ ``> <``\ *operand0*\ ``>, <``\ *operand1*\ ``>,... <``\ *modifier0*\ ``> <``\ *modifier1*\ ``>...`` -Note that operands are normally comma-separated while modifiers are space-separated. +:doc:`Operands<AMDGPUOperandSyntax>` are normally comma-separated while +:doc:`modifiers<AMDGPUModifierSyntax>` are space-separated. -The order of operands and modifiers is fixed. Most modifiers are optional and may be omitted. +The order of *operands* and *modifiers* is fixed. +Most *modifiers* are optional and may be omitted. -See detailed instruction syntax description for :doc:`GFX7<AMDGPUAsmGFX7>`, -:doc:`GFX8<AMDGPUAsmGFX8>` and :doc:`GFX9<AMDGPUAsmGFX9>`. +See detailed instruction syntax description for :doc:`GFX7<AMDGPU/AMDGPUAsmGFX7>`, +:doc:`GFX8<AMDGPU/AMDGPUAsmGFX8>` and :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>`. Note that features under development are not included in this description. @@ -4583,22 +4588,12 @@ operands, refer to one of instruction set architecture manuals Operands ~~~~~~~~ -The following syntax for register operands is supported: - -* SGPR registers: s0, ... or s[0], ... -* VGPR registers: v0, ... or v[0], ... -* TTMP registers: ttmp0, ... or ttmp[0], ... -* Special registers: exec (exec_lo, exec_hi), vcc (vcc_lo, vcc_hi), flat_scratch (flat_scratch_lo, flat_scratch_hi) -* Special trap registers: tba (tba_lo, tba_hi), tma (tma_lo, tma_hi) -* Register pairs, quads, etc: s[2:3], v[10:11], ttmp[5:6], s[4:7], v[12:15], ttmp[4:7], s[8:15], ... -* Register lists: [s0, s1], [ttmp0, ttmp1, ttmp2, ttmp3] -* Register index expressions: v[2*2], s[1-1:2-1] -* 'off' indicates that an operand is not enabled +Detailed description of operands may be found :doc:`here<AMDGPUOperandSyntax>`. Modifiers ~~~~~~~~~ -Detailed description of modifiers may be found :doc:`here<AMDGPUOperandSyntax>`. +Detailed description of modifiers may be found :doc:`here<AMDGPUModifierSyntax>`. Instruction Examples ~~~~~~~~~~~~~~~~~~~~ |
