summaryrefslogtreecommitdiffstats
path: root/llvm/docs/AMDGPUModifierSyntax.rst
diff options
context:
space:
mode:
authorHiroshi Inoue <inouehrs@jp.ibm.com>2018-12-28 08:00:39 +0000
committerHiroshi Inoue <inouehrs@jp.ibm.com>2018-12-28 08:00:39 +0000
commit1ea98f040ea4281878bdd6474af6aab3462735f9 (patch)
tree45f578f87636f392608002caabd1061cd4b3d5d8 /llvm/docs/AMDGPUModifierSyntax.rst
parent530ff8f3ccc4bcf9acb27c0dff235e3f3616c675 (diff)
downloadbcm5719-llvm-1ea98f040ea4281878bdd6474af6aab3462735f9.tar.gz
bcm5719-llvm-1ea98f040ea4281878bdd6474af6aab3462735f9.zip
[PowerPC] handle ISD:TRUNCATE in BitPermutationSelector
This is the last one in a series of patches to support better code generation for bitfield insert. BitPermutationSelector already support ISD::ZERO_EXTEND but not TRUNCATE. This patch adds support for ISD:TRUNCATE in BitPermutationSelector. For example of this test case, struct s64b { int a:4; int b:16; int c:24; }; void bitfieldinsert64b(struct s64b *p, unsigned char v) { p->b = v; } the selection DAG loos like: t14: i32,ch = load<(load 4 from %ir.0)> t0, t2, undef:i64 t18: i32 = and t14, Constant:i32<-1048561> t4: i64,ch = CopyFromReg t0, Register:i64 %1 t22: i64 = AssertZext t4, ValueType:ch:i8 t23: i32 = truncate t22 t16: i32 = shl nuw nsw t23, Constant:i32<4> t19: i32 = or t18, t16 t20: ch = store<(store 4 into %ir.0)> t14:1, t19, t2, undef:i64 By handling truncate in the BitPermutationSelector, we can use information from AssertZext when selecting t19 and skip the mask operation corresponding to t18. So the generated sequences with and without this patch are without this patch rlwinm 5, 5, 0, 28, 11 # corresponding to t18 rlwimi 5, 4, 4, 20, 27 with this patch rlwimi 5, 4, 4, 12, 27 Differential Revision: https://reviews.llvm.org/D49076 llvm-svn: 350118
Diffstat (limited to 'llvm/docs/AMDGPUModifierSyntax.rst')
0 files changed, 0 insertions, 0 deletions
OpenPOWER on IntegriCloud