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| author | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2019-09-25 12:38:35 +0000 |
|---|---|---|
| committer | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2019-09-25 12:38:35 +0000 |
| commit | b9683d3c53d6043d7cbeabf451860c027557be96 (patch) | |
| tree | 0de79b556f9ce1e73677da72af51dfd295c1d830 /llvm/docs/AMDGPU | |
| parent | 20f4afc5a74b77bae7964be839074544e09c9c19 (diff) | |
| download | bcm5719-llvm-b9683d3c53d6043d7cbeabf451860c027557be96.tar.gz bcm5719-llvm-b9683d3c53d6043d7cbeabf451860c027557be96.zip | |
[AMDGPU][MC][DOC] Updated AMD GPU assembler description.
Summary of changes:
- Updated to reflect recent changes in assembler;
- Minor bugfixing and improvements.
llvm-svn: 372857
Diffstat (limited to 'llvm/docs/AMDGPU')
56 files changed, 618 insertions, 320 deletions
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst index 9c762aa0f83..a0e514e29b2 100644 --- a/llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst +++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst @@ -566,7 +566,7 @@ SOPC s_cmp_lg_u64 :ref:`ssrc0<amdgpu_synid8_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid8_ssrc64_0>` s_cmp_lt_i32 :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid8_ssrc32_0>` s_cmp_lt_u32 :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid8_ssrc32_0>` - s_set_gpr_idx_on :ref:`ssrc<amdgpu_synid8_ssrc32_0>`, :ref:`imm4<amdgpu_synid8_imm4>` + s_set_gpr_idx_on :ref:`ssrc<amdgpu_synid8_ssrc32_0>`, :ref:`imask<amdgpu_synid8_imask>` s_setvskip :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid8_ssrc32_0>` SOPK @@ -624,7 +624,7 @@ SOPP s_nop :ref:`imm16<amdgpu_synid8_bimm16>` s_sendmsg :ref:`msg<amdgpu_synid8_msg>` s_sendmsghalt :ref:`msg<amdgpu_synid8_msg>` - s_set_gpr_idx_mode :ref:`imm4<amdgpu_synid8_imm4>` + s_set_gpr_idx_mode :ref:`imask<amdgpu_synid8_imask>` s_set_gpr_idx_off s_sethalt :ref:`imm16<amdgpu_synid8_bimm16>` s_setkill :ref:`imm16<amdgpu_synid8_bimm16>` @@ -1756,7 +1756,7 @@ VOPC gfx8_fimm16 gfx8_fimm32 gfx8_hwreg - gfx8_imm4 + gfx8_imask gfx8_label gfx8_msg gfx8_param diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst index 3ffb9fd5c8d..8ce056c8caf 100644 --- a/llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst +++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst @@ -736,7 +736,7 @@ SOPC s_cmp_lg_u64 :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc64_0>` s_cmp_lt_i32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>` s_cmp_lt_u32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>` - s_set_gpr_idx_on :ref:`ssrc<amdgpu_synid9_ssrc32_0>`, :ref:`imm4<amdgpu_synid9_imm4>` + s_set_gpr_idx_on :ref:`ssrc<amdgpu_synid9_ssrc32_0>`, :ref:`imask<amdgpu_synid9_imask>` s_setvskip :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>` SOPK @@ -796,7 +796,7 @@ SOPP s_nop :ref:`imm16<amdgpu_synid9_bimm16>` s_sendmsg :ref:`msg<amdgpu_synid9_msg>` s_sendmsghalt :ref:`msg<amdgpu_synid9_msg>` - s_set_gpr_idx_mode :ref:`imm4<amdgpu_synid9_imm4>` + s_set_gpr_idx_mode :ref:`imask<amdgpu_synid9_imask>` s_set_gpr_idx_off s_sethalt :ref:`imm16<amdgpu_synid9_bimm16>` s_setkill :ref:`imm16<amdgpu_synid9_bimm16>` @@ -2010,7 +2010,7 @@ VOPC gfx9_fimm16 gfx9_fimm32 gfx9_hwreg - gfx9_imm4 + gfx9_imask gfx9_label gfx9_msg gfx9_param diff --git a/llvm/docs/AMDGPU/gfx10_bimm16.rst b/llvm/docs/AMDGPU/gfx10_bimm16.rst index 00e9b71b92e..689ac46d94b 100644 --- a/llvm/docs/AMDGPU/gfx10_bimm16.rst +++ b/llvm/docs/AMDGPU/gfx10_bimm16.rst @@ -10,5 +10,5 @@ imm16 =========================== -An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits. +A 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535. diff --git a/llvm/docs/AMDGPU/gfx10_bimm32.rst b/llvm/docs/AMDGPU/gfx10_bimm32.rst index c4b87df907f..7e1bd334ebf 100644 --- a/llvm/docs/AMDGPU/gfx10_bimm32.rst +++ b/llvm/docs/AMDGPU/gfx10_bimm32.rst @@ -10,5 +10,5 @@ imm32 =========================== -An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 32 bits. +An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value is truncated to 32 bits. diff --git a/llvm/docs/AMDGPU/gfx10_data_mimg_atomic_cmp.rst b/llvm/docs/AMDGPU/gfx10_data_mimg_atomic_cmp.rst index bd257cf570b..6b5cd681435 100644 --- a/llvm/docs/AMDGPU/gfx10_data_mimg_atomic_cmp.rst +++ b/llvm/docs/AMDGPU/gfx10_data_mimg_atomic_cmp.rst @@ -21,7 +21,7 @@ Optionally may serve as an output data: * :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword. * :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified. - Note. The surface data format is indicated in the image resource constant but not in the instruction. + Note: the surface data format is indicated in the image resource constant but not in the instruction. *Operands:* :ref:`v<amdgpu_synid_v>` diff --git a/llvm/docs/AMDGPU/gfx10_data_mimg_atomic_reg.rst b/llvm/docs/AMDGPU/gfx10_data_mimg_atomic_reg.rst index 930dab31321..7b74290a565 100644 --- a/llvm/docs/AMDGPU/gfx10_data_mimg_atomic_reg.rst +++ b/llvm/docs/AMDGPU/gfx10_data_mimg_atomic_reg.rst @@ -21,6 +21,6 @@ Optionally may serve as an output data: * :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword. * :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified. - Note. The surface data format is indicated in the image resource constant but not in the instruction. + Note: the surface data format is indicated in the image resource constant but not in the instruction. *Operands:* :ref:`v<amdgpu_synid_v>` diff --git a/llvm/docs/AMDGPU/gfx10_fimm16.rst b/llvm/docs/AMDGPU/gfx10_fimm16.rst index c4d85be860d..5c1dccc4689 100644 --- a/llvm/docs/AMDGPU/gfx10_fimm16.rst +++ b/llvm/docs/AMDGPU/gfx10_fimm16.rst @@ -10,5 +10,6 @@ imm32 =========================== -An :ref:`integer_number<amdgpu_synid_integer_number>` or a :ref:`floating-point_number<amdgpu_synid_floating-point_number>`. The number is converted to *f16* as described :ref:`here<amdgpu_synid_lit_conv>`. +A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. +The value is converted to *f16* as described :ref:`here<amdgpu_synid_fp_conv>`. diff --git a/llvm/docs/AMDGPU/gfx10_fimm32.rst b/llvm/docs/AMDGPU/gfx10_fimm32.rst index 7ff84cc051b..258762c4ed7 100644 --- a/llvm/docs/AMDGPU/gfx10_fimm32.rst +++ b/llvm/docs/AMDGPU/gfx10_fimm32.rst @@ -10,5 +10,6 @@ imm32 =========================== -An :ref:`integer_number<amdgpu_synid_integer_number>` or a :ref:`floating-point_number<amdgpu_synid_floating-point_number>`. The value is converted to *f32* as described :ref:`here<amdgpu_synid_lit_conv>`. +A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. +The value is converted to *f32* as described :ref:`here<amdgpu_synid_fp_conv>`. diff --git a/llvm/docs/AMDGPU/gfx10_hwreg.rst b/llvm/docs/AMDGPU/gfx10_hwreg.rst index 64d441bc72f..56e2c66cbcf 100644 --- a/llvm/docs/AMDGPU/gfx10_hwreg.rst +++ b/llvm/docs/AMDGPU/gfx10_hwreg.rst @@ -14,18 +14,21 @@ Bits of a hardware register being accessed. The bits of this operand have the following meaning: - ============ =================================== - Bits Description - ============ =================================== - 5:0 Register *id*. - 10:6 First bit *offset* (0..31). - 15:11 *Size* in bits (1..32). - ============ =================================== + ======= ===================== ============ + Bits Description Value Range + ======= ===================== ============ + 5:0 Register *id*. 0..63 + 10:6 First bit *offset*. 0..31 + 15:11 *Size* in bits. 1..32 + ======= ===================== ============ -This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below. +This operand may be specified as one of the following: + +* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF. +* An *hwreg* value described below. ==================================== ============================================================================ - Syntax Description + Hwreg Value Syntax Description ==================================== ============================================================================ hwreg({0..63}) All bits of a register indicated by its *id*. hwreg(<*name*>) All bits of a register indicated by its *name*. @@ -33,7 +36,8 @@ This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_s hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by register *name*, first bit *offset* and *size*. ==================================== ============================================================================ -Register *id*, *offset* and *size* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`. +Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>` +or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`. Defined register *names* include: @@ -62,7 +66,16 @@ Examples: .. parsed-literal:: - s_getreg_b32 s2, 0x6 + reg = 1 + offset = 2 + size = 4 + hwreg_enc = reg | (offset << 6) | ((size - 1) << 11) + + s_getreg_b32 s2, 0x1881 + s_getreg_b32 s2, hwreg_enc // the same as above + s_getreg_b32 s2, hwreg(1, 2, 4) // the same as above + s_getreg_b32 s2, hwreg(reg, offset, size) // the same as above + s_getreg_b32 s2, hwreg(15) s_getreg_b32 s2, hwreg(51, 1, 31) s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) diff --git a/llvm/docs/AMDGPU/gfx10_label.rst b/llvm/docs/AMDGPU/gfx10_label.rst index 288c6c023a5..40c973eaf67 100644 --- a/llvm/docs/AMDGPU/gfx10_label.rst +++ b/llvm/docs/AMDGPU/gfx10_label.rst @@ -12,19 +12,26 @@ label A branch target which is a 16-bit signed integer treated as a PC-relative dword offset. -This operand may be specified as: +This operand may be specified as one of the following: -* An :ref:`integer_number<amdgpu_synid_integer_number>`. The number is truncated to 16 bits. -* An :ref:`absolute_expression<amdgpu_synid_absolute_expression>` which must start with an :ref:`integer_number<amdgpu_synid_integer_number>`. The value of the expression is truncated to 16 bits. -* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label). The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker. +* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535. +* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label) representing a relocatable address in the same compilation unit where it is referred from. The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker. Examples: .. parsed-literal:: offset = 30 - s_branch loop_end - s_branch 2 + offset + label_1: + label_2 = . + 4 + s_branch 32 - loop_end: + s_branch offset + 2 + s_branch label_1 + s_branch label_2 + s_branch label_3 + s_branch label_4 + + label_3 = label_2 + 4 + label_4: diff --git a/llvm/docs/AMDGPU/gfx10_msg.rst b/llvm/docs/AMDGPU/gfx10_msg.rst index ef531a14db1..3e6c532dd85 100644 --- a/llvm/docs/AMDGPU/gfx10_msg.rst +++ b/llvm/docs/AMDGPU/gfx10_msg.rst @@ -12,24 +12,29 @@ msg A 16-bit message code. The bits of this operand have the following meaning: - ============ ====================================================== - Bits Description - ============ ====================================================== - 3:0 Message *type*. - 6:4 Optional *operation*. - 9:7 Optional *parameters*. - 15:10 Unused. - ============ ====================================================== - -This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below: - - ======================================== ======================================================================== - Syntax Description - ======================================== ======================================================================== - sendmsg(<*type*>) A message identified by its *type*. - sendmsg(<*type*>, <*op*>) A message identified by its *type* and *operation*. - sendmsg(<*type*>, <*op*>, <*stream*>) A message identified by its *type* and *operation* with a stream *id*. - ======================================== ======================================================================== + ============ =============================== =============== + Bits Description Value Range + ============ =============================== =============== + 3:0 Message *type*. 0..15 + 6:4 Optional *operation*. 0..7 + 7:7 Unused. \- + 9:8 Optional *stream*. 0..3 + 15:10 Unused. \- + ============ =============================== =============== + +This operand may be specified as one of the following: + +* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF. +* A *sendmsg* value described below. + + ==================================== ==================================================== + Sendmsg Value Syntax Description + ==================================== ==================================================== + sendmsg(<*type*>) A message identified by its *type*. + sendmsg(<*type*>,<*op*>) A message identified by its *type* and *operation*. + sendmsg(<*type*>,<*op*>,<*stream*>) A message identified by its *type* and *operation* + with a stream *id*. + ==================================== ==================================================== *Type* may be specified using message *name* or message *id*. @@ -37,7 +42,8 @@ This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_s Stream *id* is an integer in the range 0..3. -Message *id*, operation *id* and stream *id* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`. +Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>` +or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`. Each message type supports specific operations: @@ -60,16 +66,32 @@ Each message type supports specific operations: \ SYSMSG_OP_TTRACE_PC 4 \- ================= ========== ============================== ============ ========== +*Sendmsg* arguments are validated depending on how *type* value is specified: + +* If message *type* is specified by name, arguments values must satisfy limitations detailed in the table above. +* If message *type* is specified as a number, each argument must not exceed corresponding value range (see the first table). + Examples: .. parsed-literal:: + // numeric message code + msg = 0x10 s_sendmsg 0x12 + s_sendmsg msg + 2 + + // sendmsg with strict arguments validation s_sendmsg sendmsg(MSG_INTERRUPT) - s_sendmsg sendmsg(MSG_GET_DOORBELL) - s_sendmsg sendmsg(2, GS_OP_CUT) s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT) s_sendmsg sendmsg(MSG_GS, 2) s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_EMIT_CUT, 1) s_sendmsg sendmsg(MSG_SYSMSG, SYSMSG_OP_TTRACE_PC) + s_sendmsg sendmsg(MSG_GET_DOORBELL) + + // sendmsg with validation of value range only + msg = 2 + op = 3 + stream = 1 + s_sendmsg sendmsg(msg, op, stream) + s_sendmsg sendmsg(2, GS_OP_CUT) diff --git a/llvm/docs/AMDGPU/gfx10_perm_smem.rst b/llvm/docs/AMDGPU/gfx10_perm_smem.rst index 879b33de1df..bc12d156651 100644 --- a/llvm/docs/AMDGPU/gfx10_perm_smem.rst +++ b/llvm/docs/AMDGPU/gfx10_perm_smem.rst @@ -12,7 +12,8 @@ imm3 A bit mask which indicates request permissions. -This operand must be specified as an :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 7 bits, but only 3 low bits are significant. +This operand must be specified as an :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. +The value is truncated to 7 bits, but only 3 low bits are significant. ============ ============================== Bit Number Description diff --git a/llvm/docs/AMDGPU/gfx10_simm16.rst b/llvm/docs/AMDGPU/gfx10_simm16.rst index eb1d171e529..365600a5b2e 100644 --- a/llvm/docs/AMDGPU/gfx10_simm16.rst +++ b/llvm/docs/AMDGPU/gfx10_simm16.rst @@ -10,5 +10,5 @@ imm16 =========================== -An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits and then sign-extended to 32 bits. +An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535. diff --git a/llvm/docs/AMDGPU/gfx10_uimm16.rst b/llvm/docs/AMDGPU/gfx10_uimm16.rst index f4bfe8c924b..8ade8dd60da 100644 --- a/llvm/docs/AMDGPU/gfx10_uimm16.rst +++ b/llvm/docs/AMDGPU/gfx10_uimm16.rst @@ -10,5 +10,5 @@ imm16 =========================== -An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits and then zero-extended to 32 bits. +An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..65535. diff --git a/llvm/docs/AMDGPU/gfx10_waitcnt.rst b/llvm/docs/AMDGPU/gfx10_waitcnt.rst index e4c4bcdc169..c861fb0113c 100644 --- a/llvm/docs/AMDGPU/gfx10_waitcnt.rst +++ b/llvm/docs/AMDGPU/gfx10_waitcnt.rst @@ -14,30 +14,31 @@ Counts of outstanding instructions to wait for. The bits of this operand have the following meaning: - ============ ====================================================== - Bits Description - ============ ====================================================== - 3:0 VM_CNT: vector memory operations count, lower bits. - 6:4 EXP_CNT: export count. - 11:8 LGKM_CNT: LDS, GDS, Constant and Message count. - 15:14 VM_CNT: vector memory operations count, upper bits. - ============ ====================================================== - -This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` -or as a combination of the following symbolic helpers: + ========== ========= ================================================ ============ + High Bits Low Bits Description Value Range + ========== ========= ================================================ ============ + 15:14 3:0 VM_CNT: vector memory operations count. 0..63 + \- 6:4 EXP_CNT: export count. 0..7 + \- 11:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..15 + ========== ========= ================================================ ============ + +This operand may be specified as one of the following: + +* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF. +* A combination of *vmcnt*, *expcnt*, *lgkmcnt* and other values described below. ====================== ====================================================================== Syntax Description ====================== ====================================================================== - vmcnt(<*N*>) VM_CNT value. *N* must not exceed the largest VM_CNT value. - expcnt(<*N*>) EXP_CNT value. *N* must not exceed the largest EXP_CNT value. - lgkmcnt(<*N*>) LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value. - vmcnt_sat(<*N*>) VM_CNT value computed as min(*N*, the largest VM_CNT value). - expcnt_sat(<*N*>) EXP_CNT value computed as min(*N*, the largest EXP_CNT value). - lgkmcnt_sat(<*N*>) LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value). + vmcnt(<*N*>) A VM_CNT value. *N* must not exceed the largest VM_CNT value. + expcnt(<*N*>) An EXP_CNT value. *N* must not exceed the largest EXP_CNT value. + lgkmcnt(<*N*>) An LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value. + vmcnt_sat(<*N*>) A VM_CNT value computed as min(*N*, the largest VM_CNT value). + expcnt_sat(<*N*>) An EXP_CNT value computed as min(*N*, the largest EXP_CNT value). + lgkmcnt_sat(<*N*>) An LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value). ====================== ====================================================================== -These helpers may be specified in any order. Ampersands and commas may be used as optional separators. +These values may be specified in any order. Spaces, ampersands and commas may be used as optional separators. *N* is either an :ref:`integer number<amdgpu_synid_integer_number>` or an @@ -47,10 +48,18 @@ Examples: .. parsed-literal:: - s_waitcnt 0 + vm_cnt = 1 + exp_cnt = 2 + lgkm_cnt = 3 + cnt = vm_cnt | (exp_cnt << 4) | (lgkm_cnt << 8) + + s_waitcnt cnt + s_waitcnt 1 | (2 << 4) | (3 << 8) // the same as above + s_waitcnt vmcnt(1) expcnt(2) lgkmcnt(3) // the same as above + s_waitcnt vmcnt(vm_cnt) expcnt(exp_cnt) lgkmcnt(lgkm_cnt) // the same as above + s_waitcnt vmcnt(1) s_waitcnt expcnt(2) lgkmcnt(3) - s_waitcnt vmcnt(1) expcnt(2) lgkmcnt(3) s_waitcnt vmcnt(1), expcnt(2), lgkmcnt(3) s_waitcnt vmcnt(1) & lgkmcnt_sat(100) & expcnt(2) diff --git a/llvm/docs/AMDGPU/gfx7_bimm16.rst b/llvm/docs/AMDGPU/gfx7_bimm16.rst index eb43f9b36a9..5f1fbc1dcd6 100644 --- a/llvm/docs/AMDGPU/gfx7_bimm16.rst +++ b/llvm/docs/AMDGPU/gfx7_bimm16.rst @@ -10,5 +10,5 @@ imm16 =========================== -An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits. +A 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535. diff --git a/llvm/docs/AMDGPU/gfx7_bimm32.rst b/llvm/docs/AMDGPU/gfx7_bimm32.rst index 4d8f89d7ae3..45d35ff7ade 100644 --- a/llvm/docs/AMDGPU/gfx7_bimm32.rst +++ b/llvm/docs/AMDGPU/gfx7_bimm32.rst @@ -10,5 +10,5 @@ imm32 =========================== -An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 32 bits. +An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value is truncated to 32 bits. diff --git a/llvm/docs/AMDGPU/gfx7_data_mimg_atomic_cmp.rst b/llvm/docs/AMDGPU/gfx7_data_mimg_atomic_cmp.rst index 82c3337aeb2..0328519d17b 100644 --- a/llvm/docs/AMDGPU/gfx7_data_mimg_atomic_cmp.rst +++ b/llvm/docs/AMDGPU/gfx7_data_mimg_atomic_cmp.rst @@ -21,7 +21,7 @@ Optionally may serve as an output data: * :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword. * :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified. - Note. The surface data format is indicated in the image resource constant but not in the instruction. + Note: the surface data format is indicated in the image resource constant but not in the instruction. *Operands:* :ref:`v<amdgpu_synid_v>` diff --git a/llvm/docs/AMDGPU/gfx7_data_mimg_atomic_reg.rst b/llvm/docs/AMDGPU/gfx7_data_mimg_atomic_reg.rst index 729548dcb87..30785e47ff9 100644 --- a/llvm/docs/AMDGPU/gfx7_data_mimg_atomic_reg.rst +++ b/llvm/docs/AMDGPU/gfx7_data_mimg_atomic_reg.rst @@ -21,6 +21,6 @@ Optionally may serve as an output data: * :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword. * :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified. - Note. The surface data format is indicated in the image resource constant but not in the instruction. + Note: the surface data format is indicated in the image resource constant but not in the instruction. *Operands:* :ref:`v<amdgpu_synid_v>` diff --git a/llvm/docs/AMDGPU/gfx7_fimm32.rst b/llvm/docs/AMDGPU/gfx7_fimm32.rst index 70c81891e97..de261aea8db 100644 --- a/llvm/docs/AMDGPU/gfx7_fimm32.rst +++ b/llvm/docs/AMDGPU/gfx7_fimm32.rst @@ -10,5 +10,6 @@ imm32 =========================== -An :ref:`integer_number<amdgpu_synid_integer_number>` or a :ref:`floating-point_number<amdgpu_synid_floating-point_number>`. The value is converted to *f32* as described :ref:`here<amdgpu_synid_lit_conv>`. +A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. +The value is converted to *f32* as described :ref:`here<amdgpu_synid_fp_conv>`. diff --git a/llvm/docs/AMDGPU/gfx7_hwreg.rst b/llvm/docs/AMDGPU/gfx7_hwreg.rst index 1e2d96417c3..b303b6ce8f9 100644 --- a/llvm/docs/AMDGPU/gfx7_hwreg.rst +++ b/llvm/docs/AMDGPU/gfx7_hwreg.rst @@ -14,18 +14,21 @@ Bits of a hardware register being accessed. The bits of this operand have the following meaning: - ============ =================================== - Bits Description - ============ =================================== - 5:0 Register *id*. - 10:6 First bit *offset* (0..31). - 15:11 *Size* in bits (1..32). - ============ =================================== + ======= ===================== ============ + Bits Description Value Range + ======= ===================== ============ + 5:0 Register *id*. 0..63 + 10:6 First bit *offset*. 0..31 + 15:11 *Size* in bits. 1..32 + ======= ===================== ============ -This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below. +This operand may be specified as one of the following: + +* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF. +* An *hwreg* value described below. ==================================== ============================================================================ - Syntax Description + Hwreg Value Syntax Description ==================================== ============================================================================ hwreg({0..63}) All bits of a register indicated by its *id*. hwreg(<*name*>) All bits of a register indicated by its *name*. @@ -33,7 +36,8 @@ This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_s hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by register *name*, first bit *offset* and *size*. ==================================== ============================================================================ -Register *id*, *offset* and *size* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`. +Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>` +or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`. Defined register *names* include: @@ -53,7 +57,16 @@ Examples: .. parsed-literal:: - s_getreg_b32 s2, 0x6 + reg = 1 + offset = 2 + size = 4 + hwreg_enc = reg | (offset << 6) | ((size - 1) << 11) + + s_getreg_b32 s2, 0x1881 + s_getreg_b32 s2, hwreg_enc // the same as above + s_getreg_b32 s2, hwreg(1, 2, 4) // the same as above + s_getreg_b32 s2, hwreg(reg, offset, size) // the same as above + s_getreg_b32 s2, hwreg(15) s_getreg_b32 s2, hwreg(51, 1, 31) s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) diff --git a/llvm/docs/AMDGPU/gfx7_label.rst b/llvm/docs/AMDGPU/gfx7_label.rst index ed2f3a41666..2f6bd68ddc3 100644 --- a/llvm/docs/AMDGPU/gfx7_label.rst +++ b/llvm/docs/AMDGPU/gfx7_label.rst @@ -12,19 +12,26 @@ label A branch target which is a 16-bit signed integer treated as a PC-relative dword offset. -This operand may be specified as: +This operand may be specified as one of the following: -* An :ref:`integer_number<amdgpu_synid_integer_number>`. The number is truncated to 16 bits. -* An :ref:`absolute_expression<amdgpu_synid_absolute_expression>` which must start with an :ref:`integer_number<amdgpu_synid_integer_number>`. The value of the expression is truncated to 16 bits. -* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label). The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker. +* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535. +* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label) representing a relocatable address in the same compilation unit where it is referred from. The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker. Examples: .. parsed-literal:: offset = 30 - s_branch loop_end - s_branch 2 + offset + label_1: + label_2 = . + 4 + s_branch 32 - loop_end: + s_branch offset + 2 + s_branch label_1 + s_branch label_2 + s_branch label_3 + s_branch label_4 + + label_3 = label_2 + 4 + label_4: diff --git a/llvm/docs/AMDGPU/gfx7_msg.rst b/llvm/docs/AMDGPU/gfx7_msg.rst index 5476053ccc1..72a895ef5b3 100644 --- a/llvm/docs/AMDGPU/gfx7_msg.rst +++ b/llvm/docs/AMDGPU/gfx7_msg.rst @@ -12,24 +12,29 @@ msg A 16-bit message code. The bits of this operand have the following meaning: - ============ ====================================================== - Bits Description - ============ ====================================================== - 3:0 Message *type*. - 6:4 Optional *operation*. - 9:7 Optional *parameters*. - 15:10 Unused. - ============ ====================================================== - -This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below: - - ======================================== ======================================================================== - Syntax Description - ======================================== ======================================================================== - sendmsg(<*type*>) A message identified by its *type*. - sendmsg(<*type*>, <*op*>) A message identified by its *type* and *operation*. - sendmsg(<*type*>, <*op*>, <*stream*>) A message identified by its *type* and *operation* with a stream *id*. - ======================================== ======================================================================== + ============ =============================== =============== + Bits Description Value Range + ============ =============================== =============== + 3:0 Message *type*. 0..15 + 6:4 Optional *operation*. 0..7 + 7:7 Unused. \- + 9:8 Optional *stream*. 0..3 + 15:10 Unused. \- + ============ =============================== =============== + +This operand may be specified as one of the following: + +* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF. +* A *sendmsg* value described below. + + ==================================== ==================================================== + Sendmsg Value Syntax Description + ==================================== ==================================================== + sendmsg(<*type*>) A message identified by its *type*. + sendmsg(<*type*>,<*op*>) A message identified by its *type* and *operation*. + sendmsg(<*type*>,<*op*>,<*stream*>) A message identified by its *type* and *operation* + with a stream *id*. + ==================================== ==================================================== *Type* may be specified using message *name* or message *id*. @@ -37,7 +42,8 @@ This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_s Stream *id* is an integer in the range 0..3. -Message *id*, operation *id* and stream *id* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`. +Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>` +or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`. Each message type supports specific operations: @@ -58,15 +64,31 @@ Each message type supports specific operations: \ SYSMSG_OP_TTRACE_PC 4 \- ================= ========== ============================== ============ ========== +*Sendmsg* arguments are validated depending on how *type* value is specified: + +* If message *type* is specified by name, arguments values must satisfy limitations detailed in the table above. +* If message *type* is specified as a number, each argument must not exceed corresponding value range (see the first table). + Examples: .. parsed-literal:: + // numeric message code + msg = 0x10 s_sendmsg 0x12 + s_sendmsg msg + 2 + + // sendmsg with strict arguments validation s_sendmsg sendmsg(MSG_INTERRUPT) - s_sendmsg sendmsg(2, GS_OP_CUT) s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT) s_sendmsg sendmsg(MSG_GS, 2) s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_EMIT_CUT, 1) s_sendmsg sendmsg(MSG_SYSMSG, SYSMSG_OP_TTRACE_PC) + // sendmsg with validation of value range only + msg = 2 + op = 3 + stream = 1 + s_sendmsg sendmsg(msg, op, stream) + s_sendmsg sendmsg(2, GS_OP_CUT) + diff --git a/llvm/docs/AMDGPU/gfx7_simm16.rst b/llvm/docs/AMDGPU/gfx7_simm16.rst index 66e560ecec8..3e5d3700863 100644 --- a/llvm/docs/AMDGPU/gfx7_simm16.rst +++ b/llvm/docs/AMDGPU/gfx7_simm16.rst @@ -10,5 +10,5 @@ imm16 =========================== -An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits and then sign-extended to 32 bits. +An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535. diff --git a/llvm/docs/AMDGPU/gfx7_uimm16.rst b/llvm/docs/AMDGPU/gfx7_uimm16.rst index bd0d4c2fb14..d8a1a20528a 100644 --- a/llvm/docs/AMDGPU/gfx7_uimm16.rst +++ b/llvm/docs/AMDGPU/gfx7_uimm16.rst @@ -10,5 +10,5 @@ imm16 =========================== -An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits and then zero-extended to 32 bits. +An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..65535. diff --git a/llvm/docs/AMDGPU/gfx7_waitcnt.rst b/llvm/docs/AMDGPU/gfx7_waitcnt.rst index 3f5e07d1649..9566e6c6732 100644 --- a/llvm/docs/AMDGPU/gfx7_waitcnt.rst +++ b/llvm/docs/AMDGPU/gfx7_waitcnt.rst @@ -14,29 +14,31 @@ Counts of outstanding instructions to wait for. The bits of this operand have the following meaning: - ============ ====================================================== - Bits Description - ============ ====================================================== - 3:0 VM_CNT: vector memory operations count. - 6:4 EXP_CNT: export count. - 12:8 LGKM_CNT: LDS, GDS, Constant and Message count. - ============ ====================================================== + ===== ================================================ ============ + Bits Description Value Range + ===== ================================================ ============ + 3:0 VM_CNT: vector memory operations count. 0..15 + 6:4 EXP_CNT: export count. 0..7 + 12:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..31 + ===== ================================================ ============ -This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` -or as a combination of the following symbolic helpers: +This operand may be specified as one of the following: + +* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF. +* A combination of *vmcnt*, *expcnt*, *lgkmcnt* and other values described below. ====================== ====================================================================== Syntax Description ====================== ====================================================================== - vmcnt(<*N*>) VM_CNT value. *N* must not exceed the largest VM_CNT value. - expcnt(<*N*>) EXP_CNT value. *N* must not exceed the largest EXP_CNT value. - lgkmcnt(<*N*>) LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value. - vmcnt_sat(<*N*>) VM_CNT value computed as min(*N*, the largest VM_CNT value). - expcnt_sat(<*N*>) EXP_CNT value computed as min(*N*, the largest EXP_CNT value). - lgkmcnt_sat(<*N*>) LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value). + vmcnt(<*N*>) A VM_CNT value. *N* must not exceed the largest VM_CNT value. + expcnt(<*N*>) An EXP_CNT value. *N* must not exceed the largest EXP_CNT value. + lgkmcnt(<*N*>) An LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value. + vmcnt_sat(<*N*>) A VM_CNT value computed as min(*N*, the largest VM_CNT value). + expcnt_sat(<*N*>) An EXP_CNT value computed as min(*N*, the largest EXP_CNT value). + lgkmcnt_sat(<*N*>) An LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value). ====================== ====================================================================== -These helpers may be specified in any order. Ampersands and commas may be used as optional separators. +These values may be specified in any order. Spaces, ampersands and commas may be used as optional separators. *N* is either an :ref:`integer number<amdgpu_synid_integer_number>` or an @@ -46,10 +48,18 @@ Examples: .. parsed-literal:: - s_waitcnt 0 + vm_cnt = 1 + exp_cnt = 2 + lgkm_cnt = 3 + cnt = vm_cnt | (exp_cnt << 4) | (lgkm_cnt << 8) + + s_waitcnt cnt + s_waitcnt 1 | (2 << 4) | (3 << 8) // the same as above + s_waitcnt vmcnt(1) expcnt(2) lgkmcnt(3) // the same as above + s_waitcnt vmcnt(vm_cnt) expcnt(exp_cnt) lgkmcnt(lgkm_cnt) // the same as above + s_waitcnt vmcnt(1) s_waitcnt expcnt(2) lgkmcnt(3) - s_waitcnt vmcnt(1) expcnt(2) lgkmcnt(3) s_waitcnt vmcnt(1), expcnt(2), lgkmcnt(3) s_waitcnt vmcnt(1) & lgkmcnt_sat(100) & expcnt(2) diff --git a/llvm/docs/AMDGPU/gfx8_bimm16.rst b/llvm/docs/AMDGPU/gfx8_bimm16.rst index ed50e558232..66875c6024f 100644 --- a/llvm/docs/AMDGPU/gfx8_bimm16.rst +++ b/llvm/docs/AMDGPU/gfx8_bimm16.rst @@ -10,5 +10,5 @@ imm16 =========================== -An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits. +A 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535. diff --git a/llvm/docs/AMDGPU/gfx8_bimm32.rst b/llvm/docs/AMDGPU/gfx8_bimm32.rst index d03c27b1732..e46bc3c7ac8 100644 --- a/llvm/docs/AMDGPU/gfx8_bimm32.rst +++ b/llvm/docs/AMDGPU/gfx8_bimm32.rst @@ -10,5 +10,5 @@ imm32 =========================== -An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 32 bits. +An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value is truncated to 32 bits. diff --git a/llvm/docs/AMDGPU/gfx8_data_mimg_atomic_cmp.rst b/llvm/docs/AMDGPU/gfx8_data_mimg_atomic_cmp.rst index 80222ead81a..237b91cadfe 100644 --- a/llvm/docs/AMDGPU/gfx8_data_mimg_atomic_cmp.rst +++ b/llvm/docs/AMDGPU/gfx8_data_mimg_atomic_cmp.rst @@ -21,7 +21,7 @@ Optionally may serve as an output data: * :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword. * :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified. - Note. The surface data format is indicated in the image resource constant but not in the instruction. + Note: the surface data format is indicated in the image resource constant but not in the instruction. *Operands:* :ref:`v<amdgpu_synid_v>` diff --git a/llvm/docs/AMDGPU/gfx8_data_mimg_atomic_reg.rst b/llvm/docs/AMDGPU/gfx8_data_mimg_atomic_reg.rst index 8baf9269b88..35bcdc379a1 100644 --- a/llvm/docs/AMDGPU/gfx8_data_mimg_atomic_reg.rst +++ b/llvm/docs/AMDGPU/gfx8_data_mimg_atomic_reg.rst @@ -21,6 +21,6 @@ Optionally may serve as an output data: * :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword. * :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified. - Note. The surface data format is indicated in the image resource constant but not in the instruction. + Note: the surface data format is indicated in the image resource constant but not in the instruction. *Operands:* :ref:`v<amdgpu_synid_v>` diff --git a/llvm/docs/AMDGPU/gfx8_fimm16.rst b/llvm/docs/AMDGPU/gfx8_fimm16.rst index 5e387f5cb77..7abd5987bcd 100644 --- a/llvm/docs/AMDGPU/gfx8_fimm16.rst +++ b/llvm/docs/AMDGPU/gfx8_fimm16.rst @@ -10,5 +10,6 @@ imm32 =========================== -An :ref:`integer_number<amdgpu_synid_integer_number>` or a :ref:`floating-point_number<amdgpu_synid_floating-point_number>`. The number is converted to *f16* as described :ref:`here<amdgpu_synid_lit_conv>`. +A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. +The value is converted to *f16* as described :ref:`here<amdgpu_synid_fp_conv>`. diff --git a/llvm/docs/AMDGPU/gfx8_fimm32.rst b/llvm/docs/AMDGPU/gfx8_fimm32.rst index e29e7704b8a..a1556557f1d 100644 --- a/llvm/docs/AMDGPU/gfx8_fimm32.rst +++ b/llvm/docs/AMDGPU/gfx8_fimm32.rst @@ -10,5 +10,6 @@ imm32 =========================== -An :ref:`integer_number<amdgpu_synid_integer_number>` or a :ref:`floating-point_number<amdgpu_synid_floating-point_number>`. The value is converted to *f32* as described :ref:`here<amdgpu_synid_lit_conv>`. +A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. +The value is converted to *f32* as described :ref:`here<amdgpu_synid_fp_conv>`. diff --git a/llvm/docs/AMDGPU/gfx8_hwreg.rst b/llvm/docs/AMDGPU/gfx8_hwreg.rst index ffa1ea5afde..87d78884911 100644 --- a/llvm/docs/AMDGPU/gfx8_hwreg.rst +++ b/llvm/docs/AMDGPU/gfx8_hwreg.rst @@ -14,18 +14,21 @@ Bits of a hardware register being accessed. The bits of this operand have the following meaning: - ============ =================================== - Bits Description - ============ =================================== - 5:0 Register *id*. - 10:6 First bit *offset* (0..31). - 15:11 *Size* in bits (1..32). - ============ =================================== + ======= ===================== ============ + Bits Description Value Range + ======= ===================== ============ + 5:0 Register *id*. 0..63 + 10:6 First bit *offset*. 0..31 + 15:11 *Size* in bits. 1..32 + ======= ===================== ============ -This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below. +This operand may be specified as one of the following: + +* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF. +* An *hwreg* value described below. ==================================== ============================================================================ - Syntax Description + Hwreg Value Syntax Description ==================================== ============================================================================ hwreg({0..63}) All bits of a register indicated by its *id*. hwreg(<*name*>) All bits of a register indicated by its *name*. @@ -33,7 +36,8 @@ This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_s hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by register *name*, first bit *offset* and *size*. ==================================== ============================================================================ -Register *id*, *offset* and *size* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`. +Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>` +or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`. Defined register *names* include: @@ -53,7 +57,16 @@ Examples: .. parsed-literal:: - s_getreg_b32 s2, 0x6 + reg = 1 + offset = 2 + size = 4 + hwreg_enc = reg | (offset << 6) | ((size - 1) << 11) + + s_getreg_b32 s2, 0x1881 + s_getreg_b32 s2, hwreg_enc // the same as above + s_getreg_b32 s2, hwreg(1, 2, 4) // the same as above + s_getreg_b32 s2, hwreg(reg, offset, size) // the same as above + s_getreg_b32 s2, hwreg(15) s_getreg_b32 s2, hwreg(51, 1, 31) s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) diff --git a/llvm/docs/AMDGPU/gfx8_imask.rst b/llvm/docs/AMDGPU/gfx8_imask.rst new file mode 100644 index 00000000000..55e9a244bdc --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_imask.rst @@ -0,0 +1,66 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid8_imask: + +imask +=========================== + +This operand is a mask which controls indexing mode for operands of subsequent instructions. +Bits 0, 1 and 2 control indexing of *src0*, *src1* and *src2*, while bit 3 controls indexing of *dst*. +Value 1 enables indexing and value 0 disables it. + + ===== ======================================== + Bit Meaning + ===== ======================================== + 0 Enables or disables *src0* indexing. + 1 Enables or disables *src1* indexing. + 2 Enables or disables *src2* indexing. + 3 Enables or disables *dst* indexing. + ===== ======================================== + +This operand may be specified as one of the following: + +* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..15. +* A *gpr_idx* value described below. + + ==================================== =========================================== + Gpr_idx Value Syntax Description + ==================================== =========================================== + gpr_idx(*<operands>*) Enable indexing for specified *operands* + and disable it for the rest. + *Operands* is a comma-separated list of + values which may include: + + * "SRC0" - enable *src0* indexing. + + * "SRC1" - enable *src1* indexing. + + * "SRC2" - enable *src2* indexing. + + * "DST" - enable *dst* indexing. + + Each of these values may be specified only + once. + + *Operands* list may be empty; this syntax + disables indexing for all operands. + ==================================== =========================================== + +Examples: + +.. parsed-literal:: + + s_set_gpr_idx_mode 0 + s_set_gpr_idx_mode gpr_idx() // the same as above + + s_set_gpr_idx_mode 15 + s_set_gpr_idx_mode gpr_idx(DST,SRC0,SRC1,SRC2) // the same as above + s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) // the same as above + + s_set_gpr_idx_mode gpr_idx(DST,SRC1) + diff --git a/llvm/docs/AMDGPU/gfx8_imm4.rst b/llvm/docs/AMDGPU/gfx8_imm4.rst deleted file mode 100644 index a03de76e86e..00000000000 --- a/llvm/docs/AMDGPU/gfx8_imm4.rst +++ /dev/null @@ -1,25 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid8_imm4: - -imm4 -=========================== - -A positive :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 4 bits. - -This operand is a mask which controls indexing mode for operands of subsequent instructions. Value 1 enables indexing and value 0 disables it. - - ============ ======================================== - Bit Meaning - ============ ======================================== - 0 Enables or disables *src0* indexing. - 1 Enables or disables *src1* indexing. - 2 Enables or disables *src2* indexing. - 3 Enables or disables *dst* indexing. - ============ ======================================== - diff --git a/llvm/docs/AMDGPU/gfx8_label.rst b/llvm/docs/AMDGPU/gfx8_label.rst index 99e384ee392..4f10c76f268 100644 --- a/llvm/docs/AMDGPU/gfx8_label.rst +++ b/llvm/docs/AMDGPU/gfx8_label.rst @@ -12,19 +12,26 @@ label A branch target which is a 16-bit signed integer treated as a PC-relative dword offset. -This operand may be specified as: +This operand may be specified as one of the following: -* An :ref:`integer_number<amdgpu_synid_integer_number>`. The number is truncated to 16 bits. -* An :ref:`absolute_expression<amdgpu_synid_absolute_expression>` which must start with an :ref:`integer_number<amdgpu_synid_integer_number>`. The value of the expression is truncated to 16 bits. -* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label). The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker. +* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535. +* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label) representing a relocatable address in the same compilation unit where it is referred from. The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker. Examples: .. parsed-literal:: offset = 30 - s_branch loop_end - s_branch 2 + offset + label_1: + label_2 = . + 4 + s_branch 32 - loop_end: + s_branch offset + 2 + s_branch label_1 + s_branch label_2 + s_branch label_3 + s_branch label_4 + + label_3 = label_2 + 4 + label_4: diff --git a/llvm/docs/AMDGPU/gfx8_msg.rst b/llvm/docs/AMDGPU/gfx8_msg.rst index 313d8e68b4b..0b0b2f30748 100644 --- a/llvm/docs/AMDGPU/gfx8_msg.rst +++ b/llvm/docs/AMDGPU/gfx8_msg.rst @@ -12,24 +12,29 @@ msg A 16-bit message code. The bits of this operand have the following meaning: - ============ ====================================================== - Bits Description - ============ ====================================================== - 3:0 Message *type*. - 6:4 Optional *operation*. - 9:7 Optional *parameters*. - 15:10 Unused. - ============ ====================================================== - -This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below: - - ======================================== ======================================================================== - Syntax Description - ======================================== ======================================================================== - sendmsg(<*type*>) A message identified by its *type*. - sendmsg(<*type*>, <*op*>) A message identified by its *type* and *operation*. - sendmsg(<*type*>, <*op*>, <*stream*>) A message identified by its *type* and *operation* with a stream *id*. - ======================================== ======================================================================== + ============ =============================== =============== + Bits Description Value Range + ============ =============================== =============== + 3:0 Message *type*. 0..15 + 6:4 Optional *operation*. 0..7 + 7:7 Unused. \- + 9:8 Optional *stream*. 0..3 + 15:10 Unused. \- + ============ =============================== =============== + +This operand may be specified as one of the following: + +* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF. +* A *sendmsg* value described below. + + ==================================== ==================================================== + Sendmsg Value Syntax Description + ==================================== ==================================================== + sendmsg(<*type*>) A message identified by its *type*. + sendmsg(<*type*>,<*op*>) A message identified by its *type* and *operation*. + sendmsg(<*type*>,<*op*>,<*stream*>) A message identified by its *type* and *operation* + with a stream *id*. + ==================================== ==================================================== *Type* may be specified using message *name* or message *id*. @@ -37,7 +42,8 @@ This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_s Stream *id* is an integer in the range 0..3. -Message *id*, operation *id* and stream *id* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`. +Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>` +or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`. Each message type supports specific operations: @@ -58,15 +64,31 @@ Each message type supports specific operations: \ SYSMSG_OP_TTRACE_PC 4 \- ================= ========== ============================== ============ ========== +*Sendmsg* arguments are validated depending on how *type* value is specified: + +* If message *type* is specified by name, arguments values must satisfy limitations detailed in the table above. +* If message *type* is specified as a number, each argument must not exceed corresponding value range (see the first table). + Examples: .. parsed-literal:: + // numeric message code + msg = 0x10 s_sendmsg 0x12 + s_sendmsg msg + 2 + + // sendmsg with strict arguments validation s_sendmsg sendmsg(MSG_INTERRUPT) - s_sendmsg sendmsg(2, GS_OP_CUT) s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT) s_sendmsg sendmsg(MSG_GS, 2) s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_EMIT_CUT, 1) s_sendmsg sendmsg(MSG_SYSMSG, SYSMSG_OP_TTRACE_PC) + // sendmsg with validation of value range only + msg = 2 + op = 3 + stream = 1 + s_sendmsg sendmsg(msg, op, stream) + s_sendmsg sendmsg(2, GS_OP_CUT) + diff --git a/llvm/docs/AMDGPU/gfx8_perm_smem.rst b/llvm/docs/AMDGPU/gfx8_perm_smem.rst index 0035ac821a7..75d02ddac79 100644 --- a/llvm/docs/AMDGPU/gfx8_perm_smem.rst +++ b/llvm/docs/AMDGPU/gfx8_perm_smem.rst @@ -12,7 +12,8 @@ imm3 A bit mask which indicates request permissions. -This operand must be specified as an :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 7 bits, but only 3 low bits are significant. +This operand must be specified as an :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. +The value is truncated to 7 bits, but only 3 low bits are significant. ============ ============================== Bit Number Description diff --git a/llvm/docs/AMDGPU/gfx8_simm16.rst b/llvm/docs/AMDGPU/gfx8_simm16.rst index 730f239b6be..86161c5400e 100644 --- a/llvm/docs/AMDGPU/gfx8_simm16.rst +++ b/llvm/docs/AMDGPU/gfx8_simm16.rst @@ -10,5 +10,5 @@ imm16 =========================== -An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits and then sign-extended to 32 bits. +An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535. diff --git a/llvm/docs/AMDGPU/gfx8_uimm16.rst b/llvm/docs/AMDGPU/gfx8_uimm16.rst index a20abcc1344..9da1c60a8a7 100644 --- a/llvm/docs/AMDGPU/gfx8_uimm16.rst +++ b/llvm/docs/AMDGPU/gfx8_uimm16.rst @@ -10,5 +10,5 @@ imm16 =========================== -An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits and then zero-extended to 32 bits. +An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..65535. diff --git a/llvm/docs/AMDGPU/gfx8_waitcnt.rst b/llvm/docs/AMDGPU/gfx8_waitcnt.rst index 4bad5941711..29b430e0741 100644 --- a/llvm/docs/AMDGPU/gfx8_waitcnt.rst +++ b/llvm/docs/AMDGPU/gfx8_waitcnt.rst @@ -14,29 +14,31 @@ Counts of outstanding instructions to wait for. The bits of this operand have the following meaning: - ============ ====================================================== - Bits Description - ============ ====================================================== - 3:0 VM_CNT: vector memory operations count. - 6:4 EXP_CNT: export count. - 11:8 LGKM_CNT: LDS, GDS, Constant and Message count. - ============ ====================================================== + ===== ================================================ ============ + Bits Description Value Range + ===== ================================================ ============ + 3:0 VM_CNT: vector memory operations count. 0..15 + 6:4 EXP_CNT: export count. 0..7 + 11:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..15 + ===== ================================================ ============ -This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` -or as a combination of the following symbolic helpers: +This operand may be specified as one of the following: + +* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF. +* A combination of *vmcnt*, *expcnt*, *lgkmcnt* and other values described below. ====================== ====================================================================== Syntax Description ====================== ====================================================================== - vmcnt(<*N*>) VM_CNT value. *N* must not exceed the largest VM_CNT value. - expcnt(<*N*>) EXP_CNT value. *N* must not exceed the largest EXP_CNT value. - lgkmcnt(<*N*>) LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value. - vmcnt_sat(<*N*>) VM_CNT value computed as min(*N*, the largest VM_CNT value). - expcnt_sat(<*N*>) EXP_CNT value computed as min(*N*, the largest EXP_CNT value). - lgkmcnt_sat(<*N*>) LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value). + vmcnt(<*N*>) A VM_CNT value. *N* must not exceed the largest VM_CNT value. + expcnt(<*N*>) An EXP_CNT value. *N* must not exceed the largest EXP_CNT value. + lgkmcnt(<*N*>) An LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value. + vmcnt_sat(<*N*>) A VM_CNT value computed as min(*N*, the largest VM_CNT value). + expcnt_sat(<*N*>) An EXP_CNT value computed as min(*N*, the largest EXP_CNT value). + lgkmcnt_sat(<*N*>) An LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value). ====================== ====================================================================== -These helpers may be specified in any order. Ampersands and commas may be used as optional separators. +These values may be specified in any order. Spaces, ampersands and commas may be used as optional separators. *N* is either an :ref:`integer number<amdgpu_synid_integer_number>` or an @@ -46,10 +48,18 @@ Examples: .. parsed-literal:: - s_waitcnt 0 + vm_cnt = 1 + exp_cnt = 2 + lgkm_cnt = 3 + cnt = vm_cnt | (exp_cnt << 4) | (lgkm_cnt << 8) + + s_waitcnt cnt + s_waitcnt 1 | (2 << 4) | (3 << 8) // the same as above + s_waitcnt vmcnt(1) expcnt(2) lgkmcnt(3) // the same as above + s_waitcnt vmcnt(vm_cnt) expcnt(exp_cnt) lgkmcnt(lgkm_cnt) // the same as above + s_waitcnt vmcnt(1) s_waitcnt expcnt(2) lgkmcnt(3) - s_waitcnt vmcnt(1) expcnt(2) lgkmcnt(3) s_waitcnt vmcnt(1), expcnt(2), lgkmcnt(3) s_waitcnt vmcnt(1) & lgkmcnt_sat(100) & expcnt(2) diff --git a/llvm/docs/AMDGPU/gfx9_bimm16.rst b/llvm/docs/AMDGPU/gfx9_bimm16.rst index 2c9dc5c5215..6e961167f47 100644 --- a/llvm/docs/AMDGPU/gfx9_bimm16.rst +++ b/llvm/docs/AMDGPU/gfx9_bimm16.rst @@ -10,5 +10,5 @@ imm16 =========================== -An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits. +A 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535. diff --git a/llvm/docs/AMDGPU/gfx9_bimm32.rst b/llvm/docs/AMDGPU/gfx9_bimm32.rst index e9b89674a2e..22286f1d272 100644 --- a/llvm/docs/AMDGPU/gfx9_bimm32.rst +++ b/llvm/docs/AMDGPU/gfx9_bimm32.rst @@ -10,5 +10,5 @@ imm32 =========================== -An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 32 bits. +An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value is truncated to 32 bits. diff --git a/llvm/docs/AMDGPU/gfx9_data_mimg_atomic_cmp.rst b/llvm/docs/AMDGPU/gfx9_data_mimg_atomic_cmp.rst index 08fe297b4f3..79d10fdb4e9 100644 --- a/llvm/docs/AMDGPU/gfx9_data_mimg_atomic_cmp.rst +++ b/llvm/docs/AMDGPU/gfx9_data_mimg_atomic_cmp.rst @@ -21,7 +21,7 @@ Optionally may serve as an output data: * :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword. * :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified. - Note. The surface data format is indicated in the image resource constant but not in the instruction. + Note: the surface data format is indicated in the image resource constant but not in the instruction. *Operands:* :ref:`v<amdgpu_synid_v>` diff --git a/llvm/docs/AMDGPU/gfx9_data_mimg_atomic_reg.rst b/llvm/docs/AMDGPU/gfx9_data_mimg_atomic_reg.rst index 2037dfd5356..6889c468d26 100644 --- a/llvm/docs/AMDGPU/gfx9_data_mimg_atomic_reg.rst +++ b/llvm/docs/AMDGPU/gfx9_data_mimg_atomic_reg.rst @@ -21,6 +21,6 @@ Optionally may serve as an output data: * :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword. * :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified. - Note. The surface data format is indicated in the image resource constant but not in the instruction. + Note: the surface data format is indicated in the image resource constant but not in the instruction. *Operands:* :ref:`v<amdgpu_synid_v>` diff --git a/llvm/docs/AMDGPU/gfx9_fimm16.rst b/llvm/docs/AMDGPU/gfx9_fimm16.rst index a438b452eec..53432d2594a 100644 --- a/llvm/docs/AMDGPU/gfx9_fimm16.rst +++ b/llvm/docs/AMDGPU/gfx9_fimm16.rst @@ -10,5 +10,6 @@ imm32 =========================== -An :ref:`integer_number<amdgpu_synid_integer_number>` or a :ref:`floating-point_number<amdgpu_synid_floating-point_number>`. The number is converted to *f16* as described :ref:`here<amdgpu_synid_lit_conv>`. +A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. +The value is converted to *f16* as described :ref:`here<amdgpu_synid_fp_conv>`. diff --git a/llvm/docs/AMDGPU/gfx9_fimm32.rst b/llvm/docs/AMDGPU/gfx9_fimm32.rst index 11103e70529..e3198735ae7 100644 --- a/llvm/docs/AMDGPU/gfx9_fimm32.rst +++ b/llvm/docs/AMDGPU/gfx9_fimm32.rst @@ -10,5 +10,6 @@ imm32 =========================== -An :ref:`integer_number<amdgpu_synid_integer_number>` or a :ref:`floating-point_number<amdgpu_synid_floating-point_number>`. The value is converted to *f32* as described :ref:`here<amdgpu_synid_lit_conv>`. +A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. +The value is converted to *f32* as described :ref:`here<amdgpu_synid_fp_conv>`. diff --git a/llvm/docs/AMDGPU/gfx9_hwreg.rst b/llvm/docs/AMDGPU/gfx9_hwreg.rst index 7ebb38b42fe..b0c70cb6ccf 100644 --- a/llvm/docs/AMDGPU/gfx9_hwreg.rst +++ b/llvm/docs/AMDGPU/gfx9_hwreg.rst @@ -14,18 +14,21 @@ Bits of a hardware register being accessed. The bits of this operand have the following meaning: - ============ =================================== - Bits Description - ============ =================================== - 5:0 Register *id*. - 10:6 First bit *offset* (0..31). - 15:11 *Size* in bits (1..32). - ============ =================================== + ======= ===================== ============ + Bits Description Value Range + ======= ===================== ============ + 5:0 Register *id*. 0..63 + 10:6 First bit *offset*. 0..31 + 15:11 *Size* in bits. 1..32 + ======= ===================== ============ -This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below. +This operand may be specified as one of the following: + +* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF. +* An *hwreg* value described below. ==================================== ============================================================================ - Syntax Description + Hwreg Value Syntax Description ==================================== ============================================================================ hwreg({0..63}) All bits of a register indicated by its *id*. hwreg(<*name*>) All bits of a register indicated by its *name*. @@ -33,7 +36,8 @@ This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_s hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by register *name*, first bit *offset* and *size*. ==================================== ============================================================================ -Register *id*, *offset* and *size* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`. +Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>` +or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`. Defined register *names* include: @@ -54,7 +58,16 @@ Examples: .. parsed-literal:: - s_getreg_b32 s2, 0x6 + reg = 1 + offset = 2 + size = 4 + hwreg_enc = reg | (offset << 6) | ((size - 1) << 11) + + s_getreg_b32 s2, 0x1881 + s_getreg_b32 s2, hwreg_enc // the same as above + s_getreg_b32 s2, hwreg(1, 2, 4) // the same as above + s_getreg_b32 s2, hwreg(reg, offset, size) // the same as above + s_getreg_b32 s2, hwreg(15) s_getreg_b32 s2, hwreg(51, 1, 31) s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) diff --git a/llvm/docs/AMDGPU/gfx9_imask.rst b/llvm/docs/AMDGPU/gfx9_imask.rst new file mode 100644 index 00000000000..22d73cb4ec0 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx9_imask.rst @@ -0,0 +1,66 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid9_imask: + +imask +=========================== + +This operand is a mask which controls indexing mode for operands of subsequent instructions. +Bits 0, 1 and 2 control indexing of *src0*, *src1* and *src2*, while bit 3 controls indexing of *dst*. +Value 1 enables indexing and value 0 disables it. + + ===== ======================================== + Bit Meaning + ===== ======================================== + 0 Enables or disables *src0* indexing. + 1 Enables or disables *src1* indexing. + 2 Enables or disables *src2* indexing. + 3 Enables or disables *dst* indexing. + ===== ======================================== + +This operand may be specified as one of the following: + +* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..15. +* A *gpr_idx* value described below. + + ==================================== =========================================== + Gpr_idx Value Syntax Description + ==================================== =========================================== + gpr_idx(*<operands>*) Enable indexing for specified *operands* + and disable it for the rest. + *Operands* is a comma-separated list of + values which may include: + + * "SRC0" - enable *src0* indexing. + + * "SRC1" - enable *src1* indexing. + + * "SRC2" - enable *src2* indexing. + + * "DST" - enable *dst* indexing. + + Each of these values may be specified only + once. + + *Operands* list may be empty; this syntax + disables indexing for all operands. + ==================================== =========================================== + +Examples: + +.. parsed-literal:: + + s_set_gpr_idx_mode 0 + s_set_gpr_idx_mode gpr_idx() // the same as above + + s_set_gpr_idx_mode 15 + s_set_gpr_idx_mode gpr_idx(DST,SRC0,SRC1,SRC2) // the same as above + s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) // the same as above + + s_set_gpr_idx_mode gpr_idx(DST,SRC1) + diff --git a/llvm/docs/AMDGPU/gfx9_imm4.rst b/llvm/docs/AMDGPU/gfx9_imm4.rst deleted file mode 100644 index b1c97fb0b29..00000000000 --- a/llvm/docs/AMDGPU/gfx9_imm4.rst +++ /dev/null @@ -1,25 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid9_imm4: - -imm4 -=========================== - -A positive :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 4 bits. - -This operand is a mask which controls indexing mode for operands of subsequent instructions. Value 1 enables indexing and value 0 disables it. - - ============ ======================================== - Bit Meaning - ============ ======================================== - 0 Enables or disables *src0* indexing. - 1 Enables or disables *src1* indexing. - 2 Enables or disables *src2* indexing. - 3 Enables or disables *dst* indexing. - ============ ======================================== - diff --git a/llvm/docs/AMDGPU/gfx9_label.rst b/llvm/docs/AMDGPU/gfx9_label.rst index 32771722f71..7348fc91488 100644 --- a/llvm/docs/AMDGPU/gfx9_label.rst +++ b/llvm/docs/AMDGPU/gfx9_label.rst @@ -12,19 +12,26 @@ label A branch target which is a 16-bit signed integer treated as a PC-relative dword offset. -This operand may be specified as: +This operand may be specified as one of the following: -* An :ref:`integer_number<amdgpu_synid_integer_number>`. The number is truncated to 16 bits. -* An :ref:`absolute_expression<amdgpu_synid_absolute_expression>` which must start with an :ref:`integer_number<amdgpu_synid_integer_number>`. The value of the expression is truncated to 16 bits. -* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label). The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker. +* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535. +* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label) representing a relocatable address in the same compilation unit where it is referred from. The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker. Examples: .. parsed-literal:: offset = 30 - s_branch loop_end - s_branch 2 + offset + label_1: + label_2 = . + 4 + s_branch 32 - loop_end: + s_branch offset + 2 + s_branch label_1 + s_branch label_2 + s_branch label_3 + s_branch label_4 + + label_3 = label_2 + 4 + label_4: diff --git a/llvm/docs/AMDGPU/gfx9_msg.rst b/llvm/docs/AMDGPU/gfx9_msg.rst index 14dff9050e6..34ede710038 100644 --- a/llvm/docs/AMDGPU/gfx9_msg.rst +++ b/llvm/docs/AMDGPU/gfx9_msg.rst @@ -12,24 +12,29 @@ msg A 16-bit message code. The bits of this operand have the following meaning: - ============ ====================================================== - Bits Description - ============ ====================================================== - 3:0 Message *type*. - 6:4 Optional *operation*. - 9:7 Optional *parameters*. - 15:10 Unused. - ============ ====================================================== - -This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below: - - ======================================== ======================================================================== - Syntax Description - ======================================== ======================================================================== - sendmsg(<*type*>) A message identified by its *type*. - sendmsg(<*type*>, <*op*>) A message identified by its *type* and *operation*. - sendmsg(<*type*>, <*op*>, <*stream*>) A message identified by its *type* and *operation* with a stream *id*. - ======================================== ======================================================================== + ============ =============================== =============== + Bits Description Value Range + ============ =============================== =============== + 3:0 Message *type*. 0..15 + 6:4 Optional *operation*. 0..7 + 7:7 Unused. \- + 9:8 Optional *stream*. 0..3 + 15:10 Unused. \- + ============ =============================== =============== + +This operand may be specified as one of the following: + +* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF. +* A *sendmsg* value described below. + + ==================================== ==================================================== + Sendmsg Value Syntax Description + ==================================== ==================================================== + sendmsg(<*type*>) A message identified by its *type*. + sendmsg(<*type*>,<*op*>) A message identified by its *type* and *operation*. + sendmsg(<*type*>,<*op*>,<*stream*>) A message identified by its *type* and *operation* + with a stream *id*. + ==================================== ==================================================== *Type* may be specified using message *name* or message *id*. @@ -37,7 +42,8 @@ This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_s Stream *id* is an integer in the range 0..3. -Message *id*, operation *id* and stream *id* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`. +Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>` +or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`. Each message type supports specific operations: @@ -60,16 +66,32 @@ Each message type supports specific operations: \ SYSMSG_OP_TTRACE_PC 4 \- ================= ========== ============================== ============ ========== +*Sendmsg* arguments are validated depending on how *type* value is specified: + +* If message *type* is specified by name, arguments values must satisfy limitations detailed in the table above. +* If message *type* is specified as a number, each argument must not exceed corresponding value range (see the first table). + Examples: .. parsed-literal:: + // numeric message code + msg = 0x10 s_sendmsg 0x12 + s_sendmsg msg + 2 + + // sendmsg with strict arguments validation s_sendmsg sendmsg(MSG_INTERRUPT) - s_sendmsg sendmsg(MSG_GET_DOORBELL) - s_sendmsg sendmsg(2, GS_OP_CUT) s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT) s_sendmsg sendmsg(MSG_GS, 2) s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_EMIT_CUT, 1) s_sendmsg sendmsg(MSG_SYSMSG, SYSMSG_OP_TTRACE_PC) + s_sendmsg sendmsg(MSG_GET_DOORBELL) + + // sendmsg with validation of value range only + msg = 2 + op = 3 + stream = 1 + s_sendmsg sendmsg(msg, op, stream) + s_sendmsg sendmsg(2, GS_OP_CUT) diff --git a/llvm/docs/AMDGPU/gfx9_perm_smem.rst b/llvm/docs/AMDGPU/gfx9_perm_smem.rst index 370fb0d67b3..d13c566789c 100644 --- a/llvm/docs/AMDGPU/gfx9_perm_smem.rst +++ b/llvm/docs/AMDGPU/gfx9_perm_smem.rst @@ -12,7 +12,8 @@ imm3 A bit mask which indicates request permissions. -This operand must be specified as an :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 7 bits, but only 3 low bits are significant. +This operand must be specified as an :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. +The value is truncated to 7 bits, but only 3 low bits are significant. ============ ============================== Bit Number Description diff --git a/llvm/docs/AMDGPU/gfx9_simm16.rst b/llvm/docs/AMDGPU/gfx9_simm16.rst index 47b200a7207..4f734a04239 100644 --- a/llvm/docs/AMDGPU/gfx9_simm16.rst +++ b/llvm/docs/AMDGPU/gfx9_simm16.rst @@ -10,5 +10,5 @@ imm16 =========================== -An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits and then sign-extended to 32 bits. +An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535. diff --git a/llvm/docs/AMDGPU/gfx9_uimm16.rst b/llvm/docs/AMDGPU/gfx9_uimm16.rst index 4d1fe1de3f2..dd3c9b4a299 100644 --- a/llvm/docs/AMDGPU/gfx9_uimm16.rst +++ b/llvm/docs/AMDGPU/gfx9_uimm16.rst @@ -10,5 +10,5 @@ imm16 =========================== -An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits and then zero-extended to 32 bits. +An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..65535. diff --git a/llvm/docs/AMDGPU/gfx9_waitcnt.rst b/llvm/docs/AMDGPU/gfx9_waitcnt.rst index 015a51ae8c3..342f8c7fdb9 100644 --- a/llvm/docs/AMDGPU/gfx9_waitcnt.rst +++ b/llvm/docs/AMDGPU/gfx9_waitcnt.rst @@ -14,30 +14,31 @@ Counts of outstanding instructions to wait for. The bits of this operand have the following meaning: - ============ ====================================================== - Bits Description - ============ ====================================================== - 3:0 VM_CNT: vector memory operations count, lower bits. - 6:4 EXP_CNT: export count. - 11:8 LGKM_CNT: LDS, GDS, Constant and Message count. - 15:14 VM_CNT: vector memory operations count, upper bits. - ============ ====================================================== - -This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` -or as a combination of the following symbolic helpers: + ========== ========= ================================================ ============ + High Bits Low Bits Description Value Range + ========== ========= ================================================ ============ + 15:14 3:0 VM_CNT: vector memory operations count. 0..63 + \- 6:4 EXP_CNT: export count. 0..7 + \- 11:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..15 + ========== ========= ================================================ ============ + +This operand may be specified as one of the following: + +* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF. +* A combination of *vmcnt*, *expcnt*, *lgkmcnt* and other values described below. ====================== ====================================================================== Syntax Description ====================== ====================================================================== - vmcnt(<*N*>) VM_CNT value. *N* must not exceed the largest VM_CNT value. - expcnt(<*N*>) EXP_CNT value. *N* must not exceed the largest EXP_CNT value. - lgkmcnt(<*N*>) LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value. - vmcnt_sat(<*N*>) VM_CNT value computed as min(*N*, the largest VM_CNT value). - expcnt_sat(<*N*>) EXP_CNT value computed as min(*N*, the largest EXP_CNT value). - lgkmcnt_sat(<*N*>) LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value). + vmcnt(<*N*>) A VM_CNT value. *N* must not exceed the largest VM_CNT value. + expcnt(<*N*>) An EXP_CNT value. *N* must not exceed the largest EXP_CNT value. + lgkmcnt(<*N*>) An LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value. + vmcnt_sat(<*N*>) A VM_CNT value computed as min(*N*, the largest VM_CNT value). + expcnt_sat(<*N*>) An EXP_CNT value computed as min(*N*, the largest EXP_CNT value). + lgkmcnt_sat(<*N*>) An LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value). ====================== ====================================================================== -These helpers may be specified in any order. Ampersands and commas may be used as optional separators. +These values may be specified in any order. Spaces, ampersands and commas may be used as optional separators. *N* is either an :ref:`integer number<amdgpu_synid_integer_number>` or an @@ -47,10 +48,18 @@ Examples: .. parsed-literal:: - s_waitcnt 0 + vm_cnt = 1 + exp_cnt = 2 + lgkm_cnt = 3 + cnt = vm_cnt | (exp_cnt << 4) | (lgkm_cnt << 8) + + s_waitcnt cnt + s_waitcnt 1 | (2 << 4) | (3 << 8) // the same as above + s_waitcnt vmcnt(1) expcnt(2) lgkmcnt(3) // the same as above + s_waitcnt vmcnt(vm_cnt) expcnt(exp_cnt) lgkmcnt(lgkm_cnt) // the same as above + s_waitcnt vmcnt(1) s_waitcnt expcnt(2) lgkmcnt(3) - s_waitcnt vmcnt(1) expcnt(2) lgkmcnt(3) s_waitcnt vmcnt(1), expcnt(2), lgkmcnt(3) s_waitcnt vmcnt(1) & lgkmcnt_sat(100) & expcnt(2) |
