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authorDmitry Preobrazhensky <dmitry.preobrazhensky@amd.com>2018-12-17 17:38:11 +0000
committerDmitry Preobrazhensky <dmitry.preobrazhensky@amd.com>2018-12-17 17:38:11 +0000
commit47eb63684d22c12b9defb99c394dbd10e26fefff (patch)
treef497778b8180320c30d0dda8125e049f5a7d1916 /llvm/docs/AMDGPU/gfx7_attr.rst
parentf700c8b25378acf912982788340f4ab10d8a15ec (diff)
downloadbcm5719-llvm-47eb63684d22c12b9defb99c394dbd10e26fefff.tar.gz
bcm5719-llvm-47eb63684d22c12b9defb99c394dbd10e26fefff.zip
[AMDGPU][MC][DOC] Updated AMD GPU assembler description
Stage 2: added detailed description of operands See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572 llvm-svn: 349368
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+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid7_attr:
+
+attr
+===========================
+
+Interpolation attribute and channel:
+
+ ============== ===================================
+ Syntax Description
+ ============== ===================================
+ attr{0..32}.x Attribute 0..32 with *x* channel.
+ attr{0..32}.y Attribute 0..32 with *y* channel.
+ attr{0..32}.z Attribute 0..32 with *z* channel.
+ attr{0..32}.w Attribute 0..32 with *w* channel.
+ ============== ===================================
+
+Examples:
+
+.. code-block:: nasm
+
+ v_interp_p1_f32 v1, v0, attr0.x
+ v_interp_p1_f32 v1, v0, attr32.w
+
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