Python compat - print statement

Make sure all print statements are compatible with Python 2 and Python3 using
the `from __future__ import print_function` statement.

Differential Revision: https://reviews.llvm.org/D56249

llvm-svn: 350307

4 files changed, 12 insertions, 5 deletions

diff --git a/llvm/bindings/python/llvm/core.py b/llvm/bindings/python/llvm/core.py
index 6b3da6d8679..43a318f2efb 100644
--- a/llvm/bindings/python/llvm/core.py
+++ b/llvm/bindings/python/llvm/core.py
@@ -6,6 +6,7 @@
 # License. See LICENSE.TXT for details.
 #
 #===------------------------------------------------------------------------===#
+from __future__ import print_function
 
 from .common import LLVMObject
 from .common import c_object_p
@@ -605,7 +606,7 @@ def register_enumerations():
     ]
     for enum_class, enum_spec in enums:
         for name, value in enum_spec:
-            print name, value
+            print(name, value)
             enum_class.register(name, value)
     return enums
 
diff --git a/llvm/bindings/python/llvm/tests/test_bitreader.py b/llvm/bindings/python/llvm/tests/test_bitreader.py
index d5850091a91..460005a2b87 100644
--- a/llvm/bindings/python/llvm/tests/test_bitreader.py
+++ b/llvm/bindings/python/llvm/tests/test_bitreader.py
@@ -1,3 +1,5 @@
+from __future__ import print_function
+
 from .base import TestBase
 from ..core import OpCode
 from ..core import MemoryBuffer
@@ -11,5 +13,5 @@ class TestBitReader(TestBase):
     def test_parse_bitcode(self):
         source = self.get_test_bc()
         m = parse_bitcode(MemoryBuffer(filename=source))
-        print m.target
-        print m.datalayout
+        print(m.target)
+        print(m.datalayout)
diff --git a/llvm/bindings/python/llvm/tests/test_core.py b/llvm/bindings/python/llvm/tests/test_core.py
index da7b635ec99..68572b50b3d 100644
--- a/llvm/bindings/python/llvm/tests/test_core.py
+++ b/llvm/bindings/python/llvm/tests/test_core.py
@@ -1,3 +1,5 @@
+from __future__ import print_function
+
 from .base import TestBase
 from ..core import MemoryBuffer
 from ..core import PassRegistry
@@ -127,7 +129,7 @@ class TestCore(TestBase):
             self.assertEqual(inst.opcode, inst_list[i][1])
             for op in range(len(inst)):
                 o = inst.get_operand(op)
-                print o.name
+                print(o.name)
                 o.dump()
             inst.dump()
             i += 1
diff --git a/llvm/bindings/python/llvm/tests/test_disassembler.py b/llvm/bindings/python/llvm/tests/test_disassembler.py
index 37a04e4fc7e..f469ffbf393 100644
--- a/llvm/bindings/python/llvm/tests/test_disassembler.py
+++ b/llvm/bindings/python/llvm/tests/test_disassembler.py
@@ -1,3 +1,5 @@
+from __future__ import print_function
+
 from .base import TestBase
 
 from ..disassembler import Disassembler, Option_UseMarkup
@@ -38,6 +40,6 @@ class TestDisassembler(TestBase):
         disassembler = Disassembler(triple)
         disassembler.set_options(Option_UseMarkup)
         count, s = disassembler.get_instruction(sequence)
-        print s
+        print(s)
         self.assertEqual(count, 4)
         self.assertEqual(s, '\tpush\t{<reg:r4>, <reg:lr>}')