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author | Tamas Berghammer <tberghammer@google.com> | 2015-05-27 12:32:28 +0000 |
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committer | Tamas Berghammer <tberghammer@google.com> | 2015-05-27 12:32:28 +0000 |
commit | bed77de0021fc670709eac1a8246febce110834d (patch) | |
tree | b70d2317ea2e899dea31ef30c4976df749539f91 /lldb | |
parent | 691a5adbdb2e6cea55b7f3ebc129eb1aa227d9d4 (diff) | |
download | bcm5719-llvm-bed77de0021fc670709eac1a8246febce110834d.tar.gz bcm5719-llvm-bed77de0021fc670709eac1a8246febce110834d.zip |
Fix write register context in EmulateInstructionARM::EmulateMOVRdRm
llvm-svn: 238312
Diffstat (limited to 'lldb')
-rw-r--r-- | lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp b/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp index 11fe9ae35fd..9634664b485 100644 --- a/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp +++ b/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp @@ -809,13 +809,13 @@ EmulateInstructionARM::EmulateMOVRdRm (const uint32_t opcode, const ARMEncoding uint32_t result = ReadCoreReg(Rm, &success); if (!success) return false; - + // The context specifies that Rm is to be moved into Rd. EmulateInstruction::Context context; - context.type = EmulateInstruction::eContextRegisterLoad; + context.type = EmulateInstruction::eContextRegisterPlusOffset; RegisterInfo dwarf_reg; GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg); - context.SetRegister (dwarf_reg); + context.SetRegisterPlusOffset (dwarf_reg, 0); if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags)) return false; |