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| author | Mirko Brkusanin <Mirko.Brkusanin@rt-rk.com> | 2019-10-23 12:24:35 +0200 |
|---|---|---|
| committer | Mirko Brkusanin <Mirko.Brkusanin@rt-rk.com> | 2019-10-23 12:24:35 +0200 |
| commit | 4b63ca1379a8a6399c3d29560623ee832c818919 (patch) | |
| tree | 1b61de736858e27c933931953ff3926ad6747c91 /lldb | |
| parent | 74a72e684849d00dbe5cc784cf05d20fd8873cdb (diff) | |
| download | bcm5719-llvm-4b63ca1379a8a6399c3d29560623ee832c818919.tar.gz bcm5719-llvm-4b63ca1379a8a6399c3d29560623ee832c818919.zip | |
[Mips] Use appropriate private label prefix based on Mips ABI
MipsMCAsmInfo was using '$' prefix for Mips32 and '.L' for Mips64
regardless of -target-abi option. By passing MCTargetOptions to MCAsmInfo
we can find out Mips ABI and pick appropriate prefix.
Tags: #llvm, #clang, #lldb
Differential Revision: https://reviews.llvm.org/D66795
Diffstat (limited to 'lldb')
3 files changed, 14 insertions, 6 deletions
diff --git a/lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp b/lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp index 28c9de2c1e9..fa9dae0c816 100644 --- a/lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp +++ b/lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp @@ -20,6 +20,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetOptions.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ScopedPrinter.h" #include "llvm/Support/TargetRegistry.h" @@ -949,8 +950,9 @@ DisassemblerLLVMC::MCDisasmInstance::Create(const char *triple, const char *cpu, if (!subtarget_info_up) return Instance(); + llvm::MCTargetOptions MCOptions; std::unique_ptr<llvm::MCAsmInfo> asm_info_up( - curr_target->createMCAsmInfo(*reg_info_up, triple)); + curr_target->createMCAsmInfo(*reg_info_up, triple, MCOptions)); if (!asm_info_up) return Instance(); @@ -1212,7 +1214,7 @@ DisassemblerLLVMC::DisassemblerLLVMC(const ArchSpec &arch, if (llvm_arch == llvm::Triple::arm) { std::string thumb_triple(thumb_arch.GetTriple().getTriple()); m_alternate_disasm_up = - MCDisasmInstance::Create(thumb_triple.c_str(), "", features_str.c_str(), + MCDisasmInstance::Create(thumb_triple.c_str(), "", features_str.c_str(), flavor, *this); if (!m_alternate_disasm_up) m_disasm_up.reset(); diff --git a/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp b/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp index 21b6296745b..b9280478826 100644 --- a/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp +++ b/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp @@ -28,6 +28,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetOptions.h" #include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetSelect.h" @@ -149,7 +150,9 @@ EmulateInstructionMIPS::EmulateInstructionMIPS( m_insn_info.reset(target->createMCInstrInfo()); assert(m_insn_info.get()); - m_asm_info.reset(target->createMCAsmInfo(*m_reg_info, triple.getTriple())); + llvm::MCTargetOptions MCOptions; + m_asm_info.reset( + target->createMCAsmInfo(*m_reg_info, triple.getTriple(), MCOptions)); m_subtype_info.reset( target->createMCSubtargetInfo(triple.getTriple(), cpu, features)); assert(m_asm_info.get() && m_subtype_info.get()); diff --git a/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp b/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp index 5fabbeb756c..4b5ca564c0c 100644 --- a/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp +++ b/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp @@ -28,6 +28,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetOptions.h" #include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetSelect.h" @@ -153,7 +154,9 @@ EmulateInstructionMIPS64::EmulateInstructionMIPS64( m_insn_info.reset(target->createMCInstrInfo()); assert(m_insn_info.get()); - m_asm_info.reset(target->createMCAsmInfo(*m_reg_info, triple.getTriple())); + llvm::MCTargetOptions MCOptions; + m_asm_info.reset( + target->createMCAsmInfo(*m_reg_info, triple.getTriple(), MCOptions)); m_subtype_info.reset( target->createMCSubtargetInfo(triple.getTriple(), cpu, features)); assert(m_asm_info.get() && m_subtype_info.get()); @@ -1360,7 +1363,7 @@ bool EmulateInstructionMIPS64::Emulate_BXX_3ops(llvm::MCInst &insn) { if (!success) return false; - if (!strcasecmp(op_name, "BEQ") || !strcasecmp(op_name, "BEQL") + if (!strcasecmp(op_name, "BEQ") || !strcasecmp(op_name, "BEQL") || !strcasecmp(op_name, "BEQ64") ) { if (rs_val == rt_val) target = pc + offset; @@ -1602,7 +1605,7 @@ bool EmulateInstructionMIPS64::Emulate_BXX_2ops(llvm::MCInst &insn) { target = pc + offset; else target = pc + 8; - } else if (!strcasecmp(op_name, "BLEZL") || !strcasecmp(op_name, "BLEZ") + } else if (!strcasecmp(op_name, "BLEZL") || !strcasecmp(op_name, "BLEZ") || !strcasecmp(op_name, "BLEZ64")) { if (rs_val <= 0) target = pc + offset; |

