Change the ftag x87 register from being 8-bits wide to 16-bits wide

to match the changes Saleem Abdulrasool committed in r311579.  Fixes
a testsuite failure now that the testsuite expects a 16 bit return
value for thsi reg.

llvm-svn: 311627

2 files changed, 8 insertions, 8 deletions

diff --git a/lldb/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp b/lldb/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp
index 6cc5ae6c36c..1a884bc4eab 100644
--- a/lldb/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp
+++ b/lldb/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp
@@ -1086,7 +1086,7 @@ const DNBRegisterInfo DNBArchImplI386::g_fpu_registers_no_avx[] = {
     {e_regSetFPU, fpu_fsw, "fstat", NULL, Uint, Hex, FPU_SIZE_UINT(fsw),
      FPU_OFFSET(fsw), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
      INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
-    {e_regSetFPU, fpu_ftw, "ftag", NULL, Uint, Hex, FPU_SIZE_UINT(ftw),
+    {e_regSetFPU, fpu_ftw, "ftag", NULL, Uint, Hex, 2 /* sizeof __fpu_ftw + sizeof __fpu_rsrv1 */,
      FPU_OFFSET(ftw), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
      INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
     {e_regSetFPU, fpu_fop, "fop", NULL, Uint, Hex, FPU_SIZE_UINT(fop),
@@ -1177,7 +1177,7 @@ const DNBRegisterInfo DNBArchImplI386::g_fpu_registers_avx[] = {
     {e_regSetFPU, fpu_fsw, "fstat", NULL, Uint, Hex, FPU_SIZE_UINT(fsw),
      AVX_OFFSET(fsw), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
      INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
-    {e_regSetFPU, fpu_ftw, "ftag", NULL, Uint, Hex, FPU_SIZE_UINT(ftw),
+    {e_regSetFPU, fpu_ftw, "ftag", NULL, Uint, Hex, 2 /* sizeof __fpu_ftw + sizeof __fpu_rsrv1 */,
      AVX_OFFSET(ftw), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
      INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
     {e_regSetFPU, fpu_fop, "fop", NULL, Uint, Hex, FPU_SIZE_UINT(fop),
@@ -1414,7 +1414,7 @@ bool DNBArchImplI386::GetRegisterValue(uint32_t set, uint32_t reg,
             *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw));
         return true;
       case fpu_ftw:
-        value->value.uint8 = m_state.context.fpu.no_avx.__fpu_ftw;
+        memcpy (&value->value.uint16, &m_state.context.fpu.no_avx.__fpu_ftw, 2);
         return true;
       case fpu_fop:
         value->value.uint16 = m_state.context.fpu.no_avx.__fpu_fop;
@@ -1607,7 +1607,7 @@ bool DNBArchImplI386::SetRegisterValue(uint32_t set, uint32_t reg,
         success = true;
         break;
       case fpu_ftw:
-        m_state.context.fpu.no_avx.__fpu_ftw = value->value.uint8;
+        memcpy (&m_state.context.fpu.no_avx.__fpu_ftw, &value->value.uint16, 2);
         success = true;
         break;
       case fpu_fop:
diff --git a/lldb/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.cpp b/lldb/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.cpp
index 416b21f2995..ccb3523fbf7 100644
--- a/lldb/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.cpp
+++ b/lldb/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.cpp
@@ -1380,7 +1380,7 @@ const DNBRegisterInfo DNBArchImplX86_64::g_fpu_registers_no_avx[] = {
      FPU_OFFSET(fcw), -1U, -1U, -1U, -1U, NULL, NULL},
     {e_regSetFPU, fpu_fsw, "fstat", NULL, Uint, Hex, FPU_SIZE_UINT(fsw),
      FPU_OFFSET(fsw), -1U, -1U, -1U, -1U, NULL, NULL},
-    {e_regSetFPU, fpu_ftw, "ftag", NULL, Uint, Hex, FPU_SIZE_UINT(ftw),
+    {e_regSetFPU, fpu_ftw, "ftag", NULL, Uint, Hex, 2 /* sizeof __fpu_ftw + sizeof __fpu_rsrv1 */,
      FPU_OFFSET(ftw), -1U, -1U, -1U, -1U, NULL, NULL},
     {e_regSetFPU, fpu_fop, "fop", NULL, Uint, Hex, FPU_SIZE_UINT(fop),
      FPU_OFFSET(fop), -1U, -1U, -1U, -1U, NULL, NULL},
@@ -1495,7 +1495,7 @@ const DNBRegisterInfo DNBArchImplX86_64::g_fpu_registers_avx[] = {
      AVX_OFFSET(fcw), -1U, -1U, -1U, -1U, NULL, NULL},
     {e_regSetFPU, fpu_fsw, "fstat", NULL, Uint, Hex, FPU_SIZE_UINT(fsw),
      AVX_OFFSET(fsw), -1U, -1U, -1U, -1U, NULL, NULL},
-    {e_regSetFPU, fpu_ftw, "ftag", NULL, Uint, Hex, FPU_SIZE_UINT(ftw),
+    {e_regSetFPU, fpu_ftw, "ftag", NULL, Uint, Hex, 2 /* sizeof __fpu_ftw + sizeof __fpu_rsrv1 */,
      AVX_OFFSET(ftw), -1U, -1U, -1U, -1U, NULL, NULL},
     {e_regSetFPU, fpu_fop, "fop", NULL, Uint, Hex, FPU_SIZE_UINT(fop),
      AVX_OFFSET(fop), -1U, -1U, -1U, -1U, NULL, NULL},
@@ -1776,7 +1776,7 @@ bool DNBArchImplX86_64::GetRegisterValue(uint32_t set, uint32_t reg,
             *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw));
         return true;
       case fpu_ftw:
-        value->value.uint8 = m_state.context.fpu.no_avx.__fpu_ftw;
+        memcpy (&value->value.uint16, &m_state.context.fpu.no_avx.__fpu_ftw, 2);
         return true;
       case fpu_fop:
         value->value.uint16 = m_state.context.fpu.no_avx.__fpu_fop;
@@ -1932,7 +1932,7 @@ bool DNBArchImplX86_64::SetRegisterValue(uint32_t set, uint32_t reg,
         success = true;
         break;
       case fpu_ftw:
-        m_state.context.fpu.no_avx.__fpu_ftw = value->value.uint8;
+        memcpy (&m_state.context.fpu.no_avx.__fpu_ftw, &value->value.uint8, 2);
         success = true;
         break;
       case fpu_fop: