X86: Change FTAG register size in FXSAVE structure

Summary:
 - Changed from 16 bits to 8 bits for Intel Architecture
    -- FXSAVE structure now conforms with the layout of FXSAVE
       area specified by IA Architecture Software Developer Manual

 - Modified Linux and FreeBSD specific files to support this change
    -- MacOSX already uses 8 bits for ftag register

 - Modified TestRegisters.py and a.cpp:
    -- Change allows 8 bit comparison of ftag values

    -- Change resolves Bug 24733:
       Removed XFAIL for Clang as the test works and passes for
       Clang compiler as well

    -- Change provides a Generic/Better way of testing Bug 24457
       and Bug 25050 by using 'int3' inline assembly in inferior

Signed-off-by: Abhishek Aggarwal <abhishek.a.aggarwal@intel.com>

Reviewers: ovyalov, jingham, clayborg

Subscribers: tfiala, emaste

Differential Revision: http://reviews.llvm.org/D13587

llvm-svn: 250022

2 files changed, 18 insertions, 10 deletions

diff --git a/lldb/test/functionalities/register/TestRegisters.py b/lldb/test/functionalities/register/TestRegisters.py
index 8957d9c84b4..32750de3806 100755
--- a/lldb/test/functionalities/register/TestRegisters.py
+++ b/lldb/test/functionalities/register/TestRegisters.py
@@ -37,7 +37,7 @@ class RegisterCommandsTestCase(TestBase):
         self.fp_register_write()
 
     @expectedFailureAndroid(archs=["i386"]) # "register read fstat" always return 0xffff
-    @expectedFailureClang("llvm.org/pr24733")
+    @skipIfFreeBSD    #llvm.org/pr25057
     def test_fp_special_purpose_register_read(self):
         """Test commands that read fpu special purpose registers."""
         if not self.getArchitecture() in ['amd64', 'i386', 'x86_64']:
@@ -165,14 +165,21 @@ class RegisterCommandsTestCase(TestBase):
         target = self.dbg.CreateTarget(exe)
         self.assertTrue(target, VALID_TARGET)
 
-        # Find the line number to break inside a.cpp.
-        self.line = line_number('a.cpp', '// Set break point at this line.')
-
-        # Set breakpoint
-        lldbutil.run_break_set_by_file_and_line (self, "a.cpp", self.line, num_expected_locations=1, loc_exact=True)
-
-        # Launch the process, and do not stop at the entry point.
-        self.runCmd ("run", RUN_SUCCEEDED)
+        # Launch the process and stop.
+        self.expect ("run", PROCESS_STOPPED, substrs = ['stopped'])
+
+        # Check stop reason; Should be either signal SIGTRAP or EXC_BREAKPOINT
+        output = self.res.GetOutput()
+        matched = False
+        substrs = ['stop reason = EXC_BREAKPOINT', 'stop reason = signal SIGTRAP']
+        for str1 in substrs:
+            matched = output.find(str1) != -1
+            with recording(self, False) as sbuf:
+                print >> sbuf, "%s sub string: %s" % ('Expecting', str1)
+                print >> sbuf, "Matched" if matched else "Not Matched"
+            if matched:
+                break
+        self.assertTrue(matched, STOPPED_DUE_TO_SIGNAL)
 
         process = target.GetProcess()
         self.assertTrue(process.GetState() == lldb.eStateStopped,
@@ -218,7 +225,7 @@ class RegisterCommandsTestCase(TestBase):
 
             # Verify ftag and save it to be used for verification in next execution of 'si' command
             self.expect("register read ftag",
-                substrs = ['ftag' + ' = ', str("0x%0.4x" % (reg_value_ftag_initial | (1<< fstat_top_pointer_initial)))])
+                substrs = ['ftag' + ' = ', str("0x%0.2x" % (reg_value_ftag_initial | (1<< fstat_top_pointer_initial)))])
             reg_value_ftag_initial = reg_value_ftag_initial | (1<< fstat_top_pointer_initial)
 
     def fp_register_write(self):
diff --git a/lldb/test/functionalities/register/a.cpp b/lldb/test/functionalities/register/a.cpp
index 587ccac3418..b659a53f09f 100755
--- a/lldb/test/functionalities/register/a.cpp
+++ b/lldb/test/functionalities/register/a.cpp
@@ -13,6 +13,7 @@ return_long_double (long double value)
 {
     float a=2, b=4,c=8, d=16, e=32, f=64, k=128, l=256, add=0;
     __asm__ (
+        "int3 ;"
         "flds %1 ;"
         "flds %2 ;"
         "flds %3 ;"