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authorJF Bastien <jfb@google.com>2015-07-01 23:41:25 +0000
committerJF Bastien <jfb@google.com>2015-07-01 23:41:25 +0000
commit03855df197944840745afd1180ebf423c7050c3c (patch)
tree10279e6f356ea28fbb0e58df4b3eb958e1471b7a /lldb/test/functionalities/thread/state
parent14cd13c51313e3a53a403eeb32b091d9c6a3011c (diff)
downloadbcm5719-llvm-03855df197944840745afd1180ebf423c7050c3c.tar.gz
bcm5719-llvm-03855df197944840745afd1180ebf423c7050c3c.zip
WebAssembly: start instructions
Summary: * Add 64-bit address space feature. * Rename SIMD feature to SIMD128. * Handle single-thread model with an IR pass (same way ARM does). * Rename generic processor to MVP, to follow design's lead. * Add bleeding-edge processors, with all features included. * Fix a few DEBUG_TYPE to match other backends. Test Plan: ninja check Reviewers: sunfish Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D10880 llvm-svn: 241211
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