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| author | Ashok Thirumurthi <ashok.thirumurthi@intel.com> | 2013-04-23 20:50:34 +0000 |
|---|---|---|
| committer | Ashok Thirumurthi <ashok.thirumurthi@intel.com> | 2013-04-23 20:50:34 +0000 |
| commit | 9ba77246ca15aa14077b9e5eb5cb768a765c072a (patch) | |
| tree | aa3436dbb040bbf087d32b0297c88ce1965d16a4 /lldb/test/functionalities/register | |
| parent | 906f2cbc65aaa0808e879a06d2ec17f38cdc8b53 (diff) | |
| download | bcm5719-llvm-9ba77246ca15aa14077b9e5eb5cb768a765c072a.tar.gz bcm5719-llvm-9ba77246ca15aa14077b9e5eb5cb768a765c072a.zip | |
Added 64-bit POSIX support to write floating-point vector registers.
- Includes tests that write, read and verify vector register content.
Reviewed by: Daniel Malea
llvm-svn: 180143
Diffstat (limited to 'lldb/test/functionalities/register')
| -rw-r--r-- | lldb/test/functionalities/register/TestRegisters.py | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/lldb/test/functionalities/register/TestRegisters.py b/lldb/test/functionalities/register/TestRegisters.py index c34f6722439..52fa9abe908 100644 --- a/lldb/test/functionalities/register/TestRegisters.py +++ b/lldb/test/functionalities/register/TestRegisters.py @@ -91,6 +91,14 @@ class RegisterCommandsTestCase(TestBase): self.expect("register read " + register, substrs = [register + ' = 0x']) + def vector_write_and_read(self, frame, register, new_value): + value = frame.FindValue(register, lldb.eValueTypeRegister) + self.assertTrue(value.IsValid(), "finding a value for register " + register) + + self.runCmd("register write " + register + " \'" + new_value + "\'") + self.expect("register read " + register, + substrs = [register + ' = ', new_value]) + def fp_register_write(self): exe = os.path.join(os.getcwd(), "a.out") @@ -121,7 +129,16 @@ class RegisterCommandsTestCase(TestBase): self.write_and_restore(currentFrame, "mxcsr") self.write_and_restore(currentFrame, "mxcsrmask") - @expectedFailureLinux # bugzilla 14661 - Expressions involving XMM registers fail on Linux + new_value = "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00}" + self.vector_write_and_read(currentFrame, "stmm0", new_value) + new_value = "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a}" + self.vector_write_and_read(currentFrame, "stmm7", new_value) + + new_value = "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x2f 0x2f}" + self.vector_write_and_read(currentFrame, "xmm0", new_value) + new_value = "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x0e 0x0f}" + self.vector_write_and_read(currentFrame, "xmm15", new_value) + def register_expressions(self): """Test expression evaluation with commands related to registers.""" self.common_setup() |

