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| author | John Brawn <john.brawn@arm.com> | 2017-02-10 17:41:08 +0000 |
|---|---|---|
| committer | John Brawn <john.brawn@arm.com> | 2017-02-10 17:41:08 +0000 |
| commit | e60f4e4b8dfe261e9dff02b1a08d80f6b34492e4 (patch) | |
| tree | 13158fc6f3883e7c422a2fe25d2ea4bd29aa16e2 /lldb/source/Plugins/UnwindAssembly | |
| parent | c8587e42571957bca663b6e42f3f7ea62a91d76c (diff) | |
| download | bcm5719-llvm-e60f4e4b8dfe261e9dff02b1a08d80f6b34492e4.tar.gz bcm5719-llvm-e60f4e4b8dfe261e9dff02b1a08d80f6b34492e4.zip | |
[ARM] Fix incorrect mask bits in MSR encoding for write_register intrinsic
In the encoding of system registers in the M-class MSR instruction the mask bits
should be 2 for registers that don't take a _<bits> qualifier (the instruction
is unpredictable otherwise), and should also be 2 if the register takes a
_<bits> qualifier but it's not present as no _<bits> is an alias for _nzcvq.
Differential Revision: https://reviews.llvm.org/D29828
llvm-svn: 294762
Diffstat (limited to 'lldb/source/Plugins/UnwindAssembly')
0 files changed, 0 insertions, 0 deletions
