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authorTim Renouf <tpr.llvm@botech.co.uk>2019-03-22 14:58:02 +0000
committerTim Renouf <tpr.llvm@botech.co.uk>2019-03-22 14:58:02 +0000
commit677387d8dc9e9821c83cb0ed93a3823e6f628307 (patch)
tree72d85eedea5d13e90337bee3d0cd21d2fb3bd162 /lldb/source/Plugins/ScriptInterpreter/Python
parentf95351b918c98ed15a742da572a42d23a1400196 (diff)
downloadbcm5719-llvm-677387d8dc9e9821c83cb0ed93a3823e6f628307.tar.gz
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[AMDGPU] Implemented dwordx3 variants of buffer/tbuffer load/store intrinsics
Now we have vec3 MVTs, this commit implements dwordx3 variants of the buffer intrinsics. On gfx6, a dwordx3 buffer load intrinsic is implemented as a dwordx4 instruction, and a dwordx3 buffer store intrinsic is not supported. We need to support the dwordx3 load intrinsic because it is generated by subtarget-unaware code in InstCombine. Differential Revision: https://reviews.llvm.org/D58904 Change-Id: I016729d8557b98a52f529638ae97c340a5922a4e llvm-svn: 356755
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