diff options
author | Craig Topper <craig.topper@intel.com> | 2019-03-22 20:46:56 +0000 |
---|---|---|
committer | Craig Topper <craig.topper@intel.com> | 2019-03-22 20:46:56 +0000 |
commit | 1ffd8e8114bc34295380b7fed815c7cf7644e84e (patch) | |
tree | 633a4626ceed2cb3f01ae34a87ca04db7c749cba /lldb/source/Plugins/ScriptInterpreter/Python | |
parent | f261638c10fafc0497bdaa3dd21a13aec3c495c3 (diff) | |
download | bcm5719-llvm-1ffd8e8114bc34295380b7fed815c7cf7644e84e.tar.gz bcm5719-llvm-1ffd8e8114bc34295380b7fed815c7cf7644e84e.zip |
[X86] Use movq for i64 atomic load on 32-bit targets when sse2 is enable
We used a lock cmpxchg8b to do i64 atomic loads. But if we have SSE2 we can do better and use a plain movq to do the load instead.
I tried to just use an f64 atomic load and add isel patterns to MOVSD(which the domain fixing pass can turn to MOVQ), but the atomic_load SDNode in TargetSelectionDAG.td requires the type to be integer.
So I've emitted VZEXT_LOAD instead which should be selected by isel to a MOVQ. Hopefully we don't need a specific atomic flavor of this. I kept the memory operand from the original AtomicSDNode. I wasn't sure if I might need to set the MOVolatile flag?
I've left some FIXMEs for improvements we can do without SSE2.
Differential Revision: https://reviews.llvm.org/D59679
llvm-svn: 356807
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python')
0 files changed, 0 insertions, 0 deletions