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authorHideki Saito <hideki.saito@intel.com>2018-04-09 23:45:40 +0000
committerHideki Saito <hideki.saito@intel.com>2018-04-09 23:45:40 +0000
commitdfa932b04942d2b53342ecddd9e1f6def9643a74 (patch)
tree109ad56e369b24eb008ee1e6827c863ee135f09f /lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.h
parentc6d2d65f37b2d9c3d219cfd48e3af3ff183767de (diff)
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[NFC][LV] Move InterleaveInfo from Legal to CostModel
Summary: Another clean up, following D43208. Interleaved memory access analysis/optimization has nothing to do with vectorization legality. It doesn't really belong there. On the other hand, cost model certainly has to know about it. In principle, vectorization should proceed like Legality ==> Optimization ==> CostModel ==> CodeGen, and this change just does that, by moving the interleaved access analysis/decision out of Legal, and run it just before CostModel object is created. After this, I can move LoopVectorizationLegality and Hints/Requirements classes into it's own header file, making it shareable within Transform tree. I have the patch already but I don't want to mix with this change. Eventual goal is to move to Analysis tree, but I first need to move RecurrenceDescriptor/InductionDescriptor from Transform/Util/LoopUtil.* to Analysis. Reviewers: rengolin, hfinkel, mkuper, dcaballe, sguggill, fhahn, aemerson Reviewed By: rengolin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45072 llvm-svn: 329645
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