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| author | Craig Topper <craig.topper@intel.com> | 2018-06-21 16:54:18 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-06-21 16:54:18 +0000 |
| commit | 8014053cbd854c864a02878350fdd0e5c615f65b (patch) | |
| tree | fe9dc15448518712a0c7a6e8d7b0285fb51141be /lldb/source/Plugins/ScriptInterpreter/Python/PythonExceptionState.h | |
| parent | dfe8fe503cbef3164d8cf3ff2eff5c7b76fb548c (diff) | |
| download | bcm5719-llvm-8014053cbd854c864a02878350fdd0e5c615f65b.tar.gz bcm5719-llvm-8014053cbd854c864a02878350fdd0e5c615f65b.zip | |
[X86] Update fast-isel tests for clang r335253.
The new IR fixes a mismatch in the final extractelement for the i32 intrinsics. Previously we extracted a 64-bit element even though we only wanted 32 bits.
SimplifyDemandedElts isn't able to make FP elements undef now and the shuffle mask I used prevents the use of horizontal add we had before. Not sure we should have been using horizontal add anyway. It's implemented on Intel with two port 5 shuffles and an add. So we have on less shuffle now, but an additional instruction to decode.
Differential Revision: https://reviews.llvm.org/D48347
llvm-svn: 335256
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/PythonExceptionState.h')
0 files changed, 0 insertions, 0 deletions
