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| author | Tim Renouf <tpr.llvm@botech.co.uk> | 2019-03-22 15:21:11 +0000 |
|---|---|---|
| committer | Tim Renouf <tpr.llvm@botech.co.uk> | 2019-03-22 15:21:11 +0000 |
| commit | 6f0191a55a53a2ac337914d670fe3f127ac65b70 (patch) | |
| tree | 2f7c003e0fcfb0503c19c54afb628c6d8bfb1760 /lldb/source/Plugins/ScriptInterpreter/Python/PythonExceptionState.h | |
| parent | 1ae5c63f35efc515309569fb0e702d705e38dbbd (diff) | |
| download | bcm5719-llvm-6f0191a55a53a2ac337914d670fe3f127ac65b70.tar.gz bcm5719-llvm-6f0191a55a53a2ac337914d670fe3f127ac65b70.zip | |
[AMDGPU] Use three- and five-dword result type in image ops
Some image ops return three or five dwords. Previously, we modeled that
with a 4 or 8 dword register class. The register allocator could
cleverly spot that some subregs were dead and allocate something else
there, but that caused the de-optimization that waitcnt insertion would
think that the result was used immediately.
This commit allows such an image op to have a result with a three or
five dword result, avoiding the above de-optimization.
Differential Revision: https://reviews.llvm.org/D58905
Change-Id: I3651211bbd7ed22721ee7b9fefd7bcc60a809d8b
llvm-svn: 356757
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/PythonExceptionState.h')
0 files changed, 0 insertions, 0 deletions
