[LLDB][MIPS] Fix offsets of all register sets and add MSA regset and FRE=1 mode support

This change :

    - Fixes offsets of all register sets for Mips.
    - Adds MSA register set and FRE=1 mode support for FP register set.
    - Separates lldb register numbers and register infos of freebsd/mips64 from linux/mips64.
    - Re-orders the register numbers of all kinds for mips to be consistent with freebsd order of register numbers.
    - Eliminates ENABLE_128_BIT_SUPPORT and union ValueData from Scalar.cpp and uses llvm::APInt and llvm::APFloat for all integer and floating point types.

Reviewers : emaste, jaydeep, clayborg
Subscribers : emaste, mohit.bhakkad, nitesh.jain, bhushan
Differential : http://reviews.llvm.org/D10919

llvm-svn: 244308

1 files changed, 2 insertions, 2 deletions

diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_mips64.cpp b/lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_mips64.cpp
index c31b0ee7de5..53fa4169bff 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_mips64.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_mips64.cpp
@@ -57,7 +57,7 @@ typedef struct _GPR
     uint64_t pc;
     uint64_t ic;
     uint64_t dummy;
-} GPR;
+} GPR_freebsd_mips;
 
 //---------------------------------------------------------------------------
 // Include RegisterInfos_mips64 to declare our g_register_infos_mips64 structure.
@@ -74,7 +74,7 @@ RegisterContextFreeBSD_mips64::RegisterContextFreeBSD_mips64(const ArchSpec &tar
 size_t
 RegisterContextFreeBSD_mips64::GetGPRSize() const
 {
-    return sizeof(GPR);
+    return sizeof(GPR_freebsd_mips);
 }
 
 const RegisterInfo *