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| author | Sagar Thakur <sagar.thakur@imgtec.com> | 2015-06-05 05:47:54 +0000 |
|---|---|---|
| committer | Sagar Thakur <sagar.thakur@imgtec.com> | 2015-06-05 05:47:54 +0000 |
| commit | 0abe018c911e3141638bb979ef731c30394e8424 (patch) | |
| tree | fc1efd981517eaae604b945c7ccf6e08599da019 /lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp | |
| parent | 785ee20cac9f7acf915cea220c3720fff83d0580 (diff) | |
| download | bcm5719-llvm-0abe018c911e3141638bb979ef731c30394e8424.tar.gz bcm5719-llvm-0abe018c911e3141638bb979ef731c30394e8424.zip | |
[lldb-server][MIPS] Read/Write FP registers in FR0 mode
Adding support for read/write FP registers in FR0 mode of mips.
Reviewers: clayborg, tberghammer, jaydeep
Subscribers: emaste, nitesh.jain, bhushan, mohit.bhakkad, lldb-commits
Differential Revision: http://reviews.llvm.org/D10242
llvm-svn: 239132
Diffstat (limited to 'lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp')
| -rw-r--r-- | lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp index 9bce8a80a22..ad8b2756ced 100644 --- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp +++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp @@ -592,6 +592,63 @@ NativeRegisterContextLinux_mips64::WriteAllRegisterValues (const lldb::DataBuffe return error; } +Error +NativeRegisterContextLinux_mips64::ReadFPR() +{ + void* buf = GetFPRBuffer(); + if (!buf) + return Error("FPR buffer is NULL"); + + Error error = NativeRegisterContextLinux::ReadFPR(); + + if (IsFR0()) + { + for (int i = 0; i < 16; i++) + { + // copy odd single from top of neighbouring even double + uint8_t * src = (uint8_t *)buf + 4 + (i * 16); + uint8_t * dst = (uint8_t *)buf + 8 + (i * 16); + *(uint32_t *) dst = *(uint32_t *) src; + } + } + + return error; +} + +Error +NativeRegisterContextLinux_mips64::WriteFPR() +{ + void* buf = GetFPRBuffer(); + if (!buf) + return Error("FPR buffer is NULL"); + + if (IsFR0()) + { + for (int i = 0; i < 16; i++) + { + // copy odd single to top of neighbouring even double + uint8_t * src = (uint8_t *)buf + 8 + (i * 16); + uint8_t * dst = (uint8_t *)buf + 4 + (i * 16); + *(uint32_t *) dst = *(uint32_t *) src; + } + } + + return NativeRegisterContextLinux::WriteFPR(); +} + +bool +NativeRegisterContextLinux_mips64::IsFR0() +{ + const RegisterInfo *const reg_info_p = GetRegisterInfoAtIndex (36); // Status Register is at index 36 of the register array + + RegisterValue reg_value; + ReadRegister (reg_info_p, reg_value); + + uint64_t value = reg_value.GetAsUInt64(); + + return (!(value & 0x4000000)); +} + bool NativeRegisterContextLinux_mips64::IsFPR(uint32_t reg_index) const { |

