Add arm64_32 support to lldb, an ILP32 codegen

that runs on arm64 ISA targets, specifically 
Apple watches.


Differential Revision: https://reviews.llvm.org/D68858

llvm-svn: 375032

1 files changed, 4 insertions, 0 deletions

diff --git a/lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp b/lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
index be02eaec2d3..fa8064690b3 100644
--- a/lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
+++ b/lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
@@ -5189,6 +5189,7 @@ lldb_private::Address ObjectFileMachO::GetEntryPointAddress() {
             }
             break;
           case llvm::MachO::CPU_TYPE_ARM64:
+          case llvm::MachO::CPU_TYPE_ARM64_32:
             if (flavor == 6) // ARM_THREAD_STATE64 from mach/arm/thread_status.h
             {
               offset += 256; // This is the offset of pc in the GPR thread state
@@ -5469,6 +5470,7 @@ ObjectFileMachO::GetThreadContextAtIndex(uint32_t idx,
 
       switch (m_header.cputype) {
       case llvm::MachO::CPU_TYPE_ARM64:
+      case llvm::MachO::CPU_TYPE_ARM64_32:
         reg_ctx_sp =
             std::make_shared<RegisterContextDarwin_arm64_Mach>(thread, data);
         break;
@@ -6029,6 +6031,7 @@ bool ObjectFileMachO::SaveCore(const lldb::ProcessSP &process_sp,
     bool make_core = false;
     switch (target_arch.GetMachine()) {
     case llvm::Triple::aarch64:
+    case llvm::Triple::aarch64_32:
     case llvm::Triple::arm:
     case llvm::Triple::thumb:
     case llvm::Triple::x86:
@@ -6131,6 +6134,7 @@ bool ObjectFileMachO::SaveCore(const lldb::ProcessSP &process_sp,
           if (thread_sp) {
             switch (mach_header.cputype) {
             case llvm::MachO::CPU_TYPE_ARM64:
+            case llvm::MachO::CPU_TYPE_ARM64_32:
               RegisterContextDarwin_arm64_Mach::Create_LC_THREAD(
                   thread_sp.get(), LC_THREAD_datas[thread_idx]);
               break;