Consolidate the knowledge of what arm cores are always executing

in thumb mode into one method in ArchSpec, replace checks for
specific cores in the disassembler with calls to this.  Also call
this from the arm instruction emulation code.

The determination of whether a given ArchSpec is thumb-only is still
a bit of a hack, but at least the hack is consolidated into a single
place.  In my original version of this patch http://reviews.llvm.org/D13578
I was calling into llvm's feature arm feature tables to make this
determination, like

#include "llvm/Support/TargetRegistry.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/../../lib/Target/ARM/ARMGenRegisterInfo.inc"
#include "llvm/../../lib/Target/ARM/ARMFeatures.h"

[...]

        std::string triple (GetTriple().getTriple());
        const char *cpu = "";
        const char *features_str = "";
        const llvm::Target *curr_target = llvm::TargetRegistry::lookupTarget(triple.c_str(), Error);
        std::unique_ptr<llvm::MCSubtargetInfo> subtarget_info_up (curr_target->createMCSubtargetInfo(triple.c_str(), cpu, features_str));
        if (subtarget_info_up->getFeatureBits()[llvm::ARM::FeatureNoARM])
        {
            return true;
        }

but those tables are post-llvm-build generated and linking against them
for all of our different build system methods was a big hiccup that I
haven't had time to revisit convincingly.

I'll keep that reviews.llvm.org patch around to remind myself that I
need to take another run at linking against the necessary tables 
again in llvm.

<rdar://problem/23022803> 

llvm-svn: 265377

1 files changed, 2 insertions, 12 deletions

diff --git a/lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp b/lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
index 5bc782c19db..ed858c1675b 100644
--- a/lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
+++ b/lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
@@ -647,18 +647,8 @@ DisassemblerLLVMC::DisassemblerLLVMC (const ArchSpec &arch, const char *flavor_s
 
     const char *triple_str = triple.getTriple().c_str();
 
-    // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
-    // 
-    // Cortex-M3 devices (e.g. armv7m) can only execute thumb (T2) instructions,
-    // so hardcode the primary disassembler to thumb mode.  Same for Cortex-M4 (armv7em).
-    //
-    // Handle the Cortex-M0 (armv6m) the same; the ISA is a subset of the T and T32
-    // instructions defined in ARMv7-A.
-
-    if ((triple.getArch() == llvm::Triple::arm || triple.getArch() == llvm::Triple::thumb)
-        && (arch.GetCore() == ArchSpec::Core::eCore_arm_armv7m
-            || arch.GetCore() == ArchSpec::Core::eCore_arm_armv7em
-            || arch.GetCore() == ArchSpec::Core::eCore_arm_armv6m))
+    // ARM Cortex M0-M7 devices only execute thumb instructions
+    if (arch.IsAlwaysThumbInstructions ())
     {
         triple_str = thumb_arch.GetTriple().getTriple().c_str();
     }