Consolidate the knowledge of what arm cores are always executing

in thumb mode into one method in ArchSpec, replace checks for
specific cores in the disassembler with calls to this.  Also call
this from the arm instruction emulation code.

The determination of whether a given ArchSpec is thumb-only is still
a bit of a hack, but at least the hack is consolidated into a single
place.  In my original version of this patch http://reviews.llvm.org/D13578
I was calling into llvm's feature arm feature tables to make this
determination, like

#include "llvm/Support/TargetRegistry.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/../../lib/Target/ARM/ARMGenRegisterInfo.inc"
#include "llvm/../../lib/Target/ARM/ARMFeatures.h"

[...]

        std::string triple (GetTriple().getTriple());
        const char *cpu = "";
        const char *features_str = "";
        const llvm::Target *curr_target = llvm::TargetRegistry::lookupTarget(triple.c_str(), Error);
        std::unique_ptr<llvm::MCSubtargetInfo> subtarget_info_up (curr_target->createMCSubtargetInfo(triple.c_str(), cpu, features_str));
        if (subtarget_info_up->getFeatureBits()[llvm::ARM::FeatureNoARM])
        {
            return true;
        }

but those tables are post-llvm-build generated and linking against them
for all of our different build system methods was a big hiccup that I
haven't had time to revisit convincingly.

I'll keep that reviews.llvm.org patch around to remind myself that I
need to take another run at linking against the necessary tables 
again in llvm.

<rdar://problem/23022803> 

llvm-svn: 265377

1 files changed, 36 insertions, 0 deletions

diff --git a/lldb/source/Core/ArchSpec.cpp b/lldb/source/Core/ArchSpec.cpp
index 0852a49c3d3..ecbd884ec52 100644
--- a/lldb/source/Core/ArchSpec.cpp
+++ b/lldb/source/Core/ArchSpec.cpp
@@ -898,6 +898,17 @@ ArchSpec::MergeFrom(const ArchSpec &other)
         if (other.TripleVendorWasSpecified())
             GetTriple().setEnvironment(other.GetTriple().getEnvironment());
     }
+    // If this and other are both arm ArchSpecs and this ArchSpec is a generic "some kind of arm"
+    // spec but the other ArchSpec is a specific arm core, adopt the specific arm core.
+    if (GetTriple().getArch() == llvm::Triple::arm
+        && other.GetTriple().getArch() == llvm::Triple::arm
+        && IsCompatibleMatch (other)
+        && GetCore() == ArchSpec::eCore_arm_generic
+        && other.GetCore() != ArchSpec::eCore_arm_generic)
+    {
+        m_core = other.GetCore();
+        CoreUpdated (true);
+    }
 }
 
 bool
@@ -1522,6 +1533,31 @@ ArchSpec::PiecewiseTripleCompare (const ArchSpec &other,
     env_different = (me.getEnvironment() != them.getEnvironment());
 }
 
+bool
+ArchSpec::IsAlwaysThumbInstructions () const
+{
+    std::string Error;
+    if (GetTriple().getArch() == llvm::Triple::arm || GetTriple().getArch() == llvm::Triple::thumb)
+    {
+        // v. https://en.wikipedia.org/wiki/ARM_Cortex-M
+        //
+        // Cortex-M0 through Cortex-M7 are ARM processor cores which can only
+        // execute thumb instructions.  We map the cores to arch names like this:
+        //
+        // Cortex-M0, Cortex-M0+, Cortex-M1:  armv6m
+        // Cortex-M3: armv7m
+        // Cortex-M4, Cortex-M7: armv7em
+
+        if (GetCore() == ArchSpec::Core::eCore_arm_armv7m
+            || GetCore() == ArchSpec::Core::eCore_arm_armv7em
+            || GetCore() == ArchSpec::Core::eCore_arm_armv6m)
+        {
+            return true;
+        }
+    }
+    return false;
+}
+
 void
 ArchSpec::DumpTriple(Stream &s) const
 {