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| author | Craig Topper <craig.topper@intel.com> | 2019-09-27 22:30:24 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-09-27 22:30:24 +0000 |
| commit | 305c811fd44182b753888059832b04ea4cbba3aa (patch) | |
| tree | 13a65d536650ebfc4de5228f297436461adc4676 /lldb/scripts/Python/python-wrapper.swig | |
| parent | d1e222e552d9f3d83083220e186c1f4c925e3e9c (diff) | |
| download | bcm5719-llvm-305c811fd44182b753888059832b04ea4cbba3aa.tar.gz bcm5719-llvm-305c811fd44182b753888059832b04ea4cbba3aa.zip | |
[X86] Add test case to show missed opportunity to turn (add (zext (vXi1 X)), Y) -> (sub Y, (sext (vXi1 X))) with avx512.
With avx512, the vXi1 type is legal. And we can more easily sign
extend them to vector registers. zext requires a sign extend and
a shift.
If we can easily turn the zext into a sext we should.
llvm-svn: 373131
Diffstat (limited to 'lldb/scripts/Python/python-wrapper.swig')
0 files changed, 0 insertions, 0 deletions
