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authorJim Grosbach <grosbach@apple.com>2011-07-29 18:47:24 +0000
committerJim Grosbach <grosbach@apple.com>2011-07-29 18:47:24 +0000
commitc4dc52cd5262e5483efc6a382a0786b52092b447 (patch)
treef3ef96654d7135edf2182f9ade7aeea85b77d9c8 /lldb/scripts/Python/modify-python-lldb.py
parentcb32ce26425632b3c91287375cc643e3aa5b01b7 (diff)
downloadbcm5719-llvm-c4dc52cd5262e5483efc6a382a0786b52092b447.tar.gz
bcm5719-llvm-c4dc52cd5262e5483efc6a382a0786b52092b447.zip
ARM assembly parsing and encoding for RFE instruction.
Fill in the missing fixed bits and the register operand bits of the instruction encoding. Refactor the definition to make the mode explicit, which is consistent with how loads and stores are normally represented and makes parsing much easier. Add parsing aliases for pseudo-instruction variants. Update the disassembler for the new representations. Add tests for parsing and encoding. llvm-svn: 136479
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