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| author | Tom Stellard <thomas.stellard@amd.com> | 2014-11-21 22:31:44 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-11-21 22:31:44 +0000 |
| commit | a99ada528c19987ae94278584bb7d4856c7ce826 (patch) | |
| tree | ce04b8b8a80660d72e1ad262fe4e30d0b4b03125 /lldb/scripts/Python/finishSwigPythonLLDB.py | |
| parent | 49a6746942e164ddd1ef8d69f0d167e508c5b770 (diff) | |
| download | bcm5719-llvm-a99ada528c19987ae94278584bb7d4856c7ce826.tar.gz bcm5719-llvm-a99ada528c19987ae94278584bb7d4856c7ce826.zip | |
R600/SI: Emit s_mov_b32 m0, -1 before every DS instruction
This s_mov_b32 will write to a virtual register from the M0Reg
class and all the ds instructions now take an extra M0Reg explicit
argument.
This change is necessary to prevent issues with the scheduler
mixing together instructions that expect different values in the m0
registers.
llvm-svn: 222583
Diffstat (limited to 'lldb/scripts/Python/finishSwigPythonLLDB.py')
0 files changed, 0 insertions, 0 deletions
