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authorAlex Bradbury <asb@lowrisc.org>2018-03-21 15:11:02 +0000
committerAlex Bradbury <asb@lowrisc.org>2018-03-21 15:11:02 +0000
commit65d6ea5e68dd5c44f39567f923820d2aef9d41b7 (patch)
tree7955e8dece5ee775ca697279f37bbe287353f947 /lldb/packages/Python
parent5dd6bd9631935f22711e633a936f489ebd9274c4 (diff)
downloadbcm5719-llvm-65d6ea5e68dd5c44f39567f923820d2aef9d41b7.tar.gz
bcm5719-llvm-65d6ea5e68dd5c44f39567f923820d2aef9d41b7.zip
[RISCV] Codegen support for RV32F floating point comparison operations
This patch also includes extensive tests targeted at select and br+fcmp IR inputs. A sequence of br+fcmp required support for FPR32 registers to be added to RISCVInstrInfo::storeRegToStackSlot and RISCVInstrInfo::loadRegFromStackSlot. llvm-svn: 328104
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