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| author | Craig Topper <craig.topper@intel.com> | 2019-03-07 21:22:56 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-03-07 21:22:56 +0000 |
| commit | d0c2dba644e27210ed13cd638aa8b8e677ed757d (patch) | |
| tree | 8f6b0772500653e0f099b1c28ac044bebae8b740 /lldb/packages/Python/lldbsuite | |
| parent | b3af5d3e57107a3bffe4c2d38b22ae96cee52245 (diff) | |
| download | bcm5719-llvm-d0c2dba644e27210ed13cd638aa8b8e677ed757d.tar.gz bcm5719-llvm-d0c2dba644e27210ed13cd638aa8b8e677ed757d.zip | |
[X86] Correct scheduler information for rotate by constant for Haswell, Broadwell, and Skylake.
Rotate with explicit immediate is a single uop from Haswell on. An immediate of 1 has a dependency on the previous writer of flags, but the other immediate values do not.
The implicit rotate by 1 instruction is 2 uops. But the flags are merged after the rotate uop so the data result does not see the flag dependency. But I don't think we have any way of modeling that.
RORX is 1 uop without the load. 2 uops with the load. We currently model these with WriteShift/WriteShiftLd.
Differential Revision: https://reviews.llvm.org/D59077
llvm-svn: 355636
Diffstat (limited to 'lldb/packages/Python/lldbsuite')
0 files changed, 0 insertions, 0 deletions
