Support nwere versions of the Segger J-Link jtag board software.

Add support in ProcessGDBRemote::GetGDBServerRegisterInfo
for recognizing a generic "arm" architecture that will be used if
nothing better is available so that we don't ignore the register
definitions if we didn't already have an architecture set.
Also in ProcessGDBRemote::DoConnectRemote don't set the target
arch unless we have a valid architecture to set it to.

Platform::ConnectProcess will try to get the current target's
architecture, or the default architecture, when creating the 
target for the connection to be attempted.  If lldb was started
with a target binary, we want to create this target with that
architecture in case the remote gdb stub doesn't supply a
qHostInfo arch.

Add logging to Target::MergeArchitecture.

<rdar://problem/34916465> 

llvm-svn: 345106

2 files changed, 154 insertions, 2 deletions

diff --git a/lldb/packages/Python/lldbsuite/test/functionalities/gdb_remote_client/TestArmRegisterDefinition.py b/lldb/packages/Python/lldbsuite/test/functionalities/gdb_remote_client/TestArmRegisterDefinition.py
new file mode 100644
index 00000000000..6e28d5b5405
--- /dev/null
+++ b/lldb/packages/Python/lldbsuite/test/functionalities/gdb_remote_client/TestArmRegisterDefinition.py
@@ -0,0 +1,130 @@
+from __future__ import print_function
+import lldb
+from lldbsuite.test.lldbtest import *
+from lldbsuite.test.decorators import *
+from gdbclientutils import *
+
+class TestArmRegisterDefinition(GDBRemoteTestBase):
+
+    @skipIfXmlSupportMissing
+    @skipIfRemote
+    def test(self):
+        """
+        Test lldb's parsing of the <architecture> tag in the target.xml register
+        description packet.
+        """
+        class MyResponder(MockGDBServerResponder):
+
+            def qXferRead(self, obj, annex, offset, length):
+                if annex == "target.xml":
+                    return """<?xml version="1.0"?>
+                        <!DOCTYPE feature SYSTEM "gdb-target.dtd">
+                        <target>
+                        <architecture>arm</architecture>
+                        <feature name="org.gnu.gdb.arm.m-profile">
+                        <reg name="r0" bitsize="32" type="uint32" group="general"/>
+                        <reg name="r1" bitsize="32" type="uint32" group="general"/>
+                        <reg name="r2" bitsize="32" type="uint32" group="general"/>
+                        <reg name="r3" bitsize="32" type="uint32" group="general"/>
+                        <reg name="r4" bitsize="32" type="uint32" group="general"/>
+                        <reg name="r5" bitsize="32" type="uint32" group="general"/>
+                        <reg name="r6" bitsize="32" type="uint32" group="general"/>
+                        <reg name="r7" bitsize="32" type="uint32" group="general"/>
+                        <reg name="r8" bitsize="32" type="uint32" group="general"/>
+                        <reg name="r9" bitsize="32" type="uint32" group="general"/>
+                        <reg name="r10" bitsize="32" type="uint32" group="general"/>
+                        <reg name="r11" bitsize="32" type="uint32" group="general"/>
+                        <reg name="r12" bitsize="32" type="uint32" group="general"/>
+                        <reg name="sp" bitsize="32" type="data_ptr" group="general"/>
+                        <reg name="lr" bitsize="32" type="uint32" group="general"/>
+                        <reg name="pc" bitsize="32" type="code_ptr" group="general"/>
+                        <reg name="xpsr" bitsize="32" regnum="25" type="uint32" group="general"/>
+                        <reg name="MSP" bitsize="32" regnum="26" type="uint32" group="general"/>
+                        <reg name="PSP" bitsize="32" regnum="27" type="uint32" group="general"/>
+                        <reg name="PRIMASK" bitsize="32" regnum="28" type="uint32" group="general"/>
+                        <reg name="BASEPRI" bitsize="32" regnum="29" type="uint32" group="general"/>
+                        <reg name="FAULTMASK" bitsize="32" regnum="30" type="uint32" group="general"/>
+                        <reg name="CONTROL" bitsize="32" regnum="31" type="uint32" group="general"/>
+                        <reg name="FPSCR" bitsize="32" type="uint32" group="float"/>
+                        <reg name="s0" bitsize="32" type="float" group="float"/>
+                        <reg name="s1" bitsize="32" type="float" group="float"/>
+                        <reg name="s2" bitsize="32" type="float" group="float"/>
+                        <reg name="s3" bitsize="32" type="float" group="float"/>
+                        <reg name="s4" bitsize="32" type="float" group="float"/>
+                        <reg name="s5" bitsize="32" type="float" group="float"/>
+                        <reg name="s6" bitsize="32" type="float" group="float"/>
+                        <reg name="s7" bitsize="32" type="float" group="float"/>
+                        <reg name="s8" bitsize="32" type="float" group="float"/>
+                        <reg name="s9" bitsize="32" type="float" group="float"/>
+                        <reg name="s10" bitsize="32" type="float" group="float"/>
+                        <reg name="s11" bitsize="32" type="float" group="float"/>
+                        <reg name="s12" bitsize="32" type="float" group="float"/>
+                        <reg name="s13" bitsize="32" type="float" group="float"/>
+                        <reg name="s14" bitsize="32" type="float" group="float"/>
+                        <reg name="s15" bitsize="32" type="float" group="float"/>
+                        <reg name="s16" bitsize="32" type="float" group="float"/>
+                        <reg name="s17" bitsize="32" type="float" group="float"/>
+                        <reg name="s18" bitsize="32" type="float" group="float"/>
+                        <reg name="s19" bitsize="32" type="float" group="float"/>
+                        <reg name="s20" bitsize="32" type="float" group="float"/>
+                        <reg name="s21" bitsize="32" type="float" group="float"/>
+                        <reg name="s22" bitsize="32" type="float" group="float"/>
+                        <reg name="s23" bitsize="32" type="float" group="float"/>
+                        <reg name="s24" bitsize="32" type="float" group="float"/>
+                        <reg name="s25" bitsize="32" type="float" group="float"/>
+                        <reg name="s26" bitsize="32" type="float" group="float"/>
+                        <reg name="s27" bitsize="32" type="float" group="float"/>
+                        <reg name="s28" bitsize="32" type="float" group="float"/>
+                        <reg name="s29" bitsize="32" type="float" group="float"/>
+                        <reg name="s30" bitsize="32" type="float" group="float"/>
+                        <reg name="s31" bitsize="32" type="float" group="float"/>
+                        </feature>
+                        </target>""", False
+                else:
+                    return None, False
+
+            def readRegister(self, regnum):
+                return "E01"
+
+            def readRegisters(self):
+                return "20000000f8360020001000002fcb0008f8360020a0360020200c0020000000000000000000000000000000000000000000000000b87f0120b7d100082ed2000800000001b87f01200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
+
+            def haltReason(self):
+                return "S05"
+
+            def qfThreadInfo(self):
+                return "mdead"
+            
+            def qC(self):
+                return ""
+
+            def qSupported(self, client_supported):
+                return "PacketSize=4000;qXfer:memory-map:read-;QStartNoAckMode+;qXfer:threads:read+;hwbreak+;qXfer:features:read+"
+
+            def QThreadSuffixSupported(self):
+                return "OK"
+
+            def QListThreadsInStopReply(self):
+                return "OK"
+
+        self.server.responder = MyResponder()
+        if self.TraceOn():
+            interp = self.dbg.GetCommandInterpreter()
+            result = lldb.SBCommandReturnObject()
+            interp.HandleCommand("log enable gdb-remote packets", result)
+        self.dbg.SetDefaultArchitecture("armv7em")
+        target = self.dbg.CreateTargetWithFileAndArch(None, None)
+
+        process = self.connect(target)
+
+        if self.TraceOn():
+            interp = self.dbg.GetCommandInterpreter()
+            result = lldb.SBCommandReturnObject()
+            interp.HandleCommand("target list", result)
+            print(result.GetOutput())
+
+        r0_valobj = process.GetThreadAtIndex(0).GetFrameAtIndex(0).FindRegister("r0")
+        self.assertEqual(r0_valobj.GetValueAsUnsigned(), 0x20)
+
+        pc_valobj = process.GetThreadAtIndex(0).GetFrameAtIndex(0).FindRegister("pc")
+        self.assertEqual(pc_valobj.GetValueAsUnsigned(), 0x0800d22e)
diff --git a/lldb/packages/Python/lldbsuite/test/functionalities/gdb_remote_client/gdbclientutils.py b/lldb/packages/Python/lldbsuite/test/functionalities/gdb_remote_client/gdbclientutils.py
index 9a81f32403d..a9e553cbb7d 100644
--- a/lldb/packages/Python/lldbsuite/test/functionalities/gdb_remote_client/gdbclientutils.py
+++ b/lldb/packages/Python/lldbsuite/test/functionalities/gdb_remote_client/gdbclientutils.py
@@ -102,12 +102,13 @@ class MockGDBServerResponder:
             return self.interrupt()
         if packet == "c":
             return self.cont()
-        if packet == "g":
+        if packet[0] == "g":
             return self.readRegisters()
         if packet[0] == "G":
             return self.writeRegisters(packet[1:])
         if packet[0] == "p":
-            return self.readRegister(int(packet[1:], 16))
+            regnum = packet[1:].split(';')[0]
+            return self.readRegister(int(regnum, 16))
         if packet[0] == "P":
             register, value = packet[1:].split("=")
             return self.readRegister(int(register, 16), value)
@@ -124,6 +125,8 @@ class MockGDBServerResponder:
             return self.qSupported(packet[11:].split(";"))
         if packet == "qfThreadInfo":
             return self.qfThreadInfo()
+        if packet == "qsThreadInfo":
+            return self.qsThreadInfo()
         if packet == "qC":
             return self.qC()
         if packet == "QEnableErrorStrings":
@@ -149,6 +152,13 @@ class MockGDBServerResponder:
         if packet.startswith("qThreadStopInfo"):
             threadnum = int (packet[15:], 16)
             return self.threadStopInfo(threadnum)
+        if packet == "QThreadSuffixSupported":
+            return self.QThreadSuffixSupported()
+        if packet == "QListThreadsInStopReply":
+            return self.QListThreadsInStopReply()
+        if packet.startswith("qMemoryRegionInfo:"):
+            return self.qMemoryRegionInfo()
+
         return self.other(packet)
 
     def interrupt(self):
@@ -184,6 +194,9 @@ class MockGDBServerResponder:
     def qfThreadInfo(self):
         return "l"
 
+    def qsThreadInfo(self):
+        return "l"
+
     def qC(self):
         return "QC0"
 
@@ -216,6 +229,15 @@ class MockGDBServerResponder:
         # empty string means unsupported
         return ""
 
+    def QThreadSuffixSupported(self):
+        return ""
+
+    def QListThreadsInStopReply(self):
+        return ""
+
+    def qMemoryRegionInfo(self):
+        return ""
+
     """
     Raised when we receive a packet for which there is no default action.
     Override the responder class to implement behavior suitable for the test at