summaryrefslogtreecommitdiffstats
path: root/lldb/packages/Python/lldbsuite/test
diff options
context:
space:
mode:
authorSaleem Abdulrasool <compnerd@compnerd.org>2017-08-23 17:23:12 +0000
committerSaleem Abdulrasool <compnerd@compnerd.org>2017-08-23 17:23:12 +0000
commitbf2a8a287814f2a50fa875420d84c1c8a99b22fc (patch)
treef856d6beca1e8e0d514dd597a385f1c707e6b9af /lldb/packages/Python/lldbsuite/test
parentfe3a5bfb25cf38d4a5d411d336af92bbfb3e79c6 (diff)
downloadbcm5719-llvm-bf2a8a287814f2a50fa875420d84c1c8a99b22fc.tar.gz
bcm5719-llvm-bf2a8a287814f2a50fa875420d84c1c8a99b22fc.zip
Process: fix FXSAVE on x86
The FXSAVE member `ftw` (FPU Tag Word) was given the wrong size (8-bit) instead of the correct width (16-bit) as per the x87 Programmer's Manual. Adjust this to ensure that we print out the complete value for the register. llvm-svn: 311579
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test')
-rw-r--r--lldb/packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/lldb/packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py b/lldb/packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py
index cc1389ca6b0..fe6ce2c25a3 100644
--- a/lldb/packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py
+++ b/lldb/packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py
@@ -256,7 +256,7 @@ class RegisterCommandsTestCase(TestBase):
self.expect(
"register read ftag", substrs=[
'ftag' + ' = ', str(
- "0x%0.2x" %
+ "0x%0.4x" %
(reg_value_ftag_initial | (
1 << fstat_top_pointer_initial)))])
reg_value_ftag_initial = reg_value_ftag_initial | (
OpenPOWER on IntegriCloud