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| author | Sander de Smalen <sander.desmalen@arm.com> | 2018-07-03 15:31:04 +0000 |
|---|---|---|
| committer | Sander de Smalen <sander.desmalen@arm.com> | 2018-07-03 15:31:04 +0000 |
| commit | 8cd1f533340e1b6f3b93577795e874fea9b6a31e (patch) | |
| tree | a3759ea508cb6bc98c587c24a1dee32aedd0b586 /lldb/packages/Python/lldbsuite/test | |
| parent | cbd224941fb3662f305c24de224ae0003d2a3b2d (diff) | |
| download | bcm5719-llvm-8cd1f533340e1b6f3b93577795e874fea9b6a31e.tar.gz bcm5719-llvm-8cd1f533340e1b6f3b93577795e874fea9b6a31e.zip | |
[AArch64][SVE] Asm: Support for FMUL (indexed)
Unpredicated FP-multiply of SVE vector with a vector-element given by
vector[index], for example:
fmul z0.s, z1.s, z2.s[0]
which performs an unpredicated FP-multiply of all 32-bit elements in
'z1' with the first element from 'z2'.
This patch adds restricted register classes for SVE vectors:
ZPR_3b (only z0..z7 are allowed) - for indexed vector of 16/32-bit elements.
ZPR_4b (only z0..z15 are allowed) - for indexed vector of 64-bit elements.
Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D48823
llvm-svn: 336205
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test')
0 files changed, 0 insertions, 0 deletions
