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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-08-27 00:08:31 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-08-27 00:08:31 +0000 |
| commit | 3b95986a32f1d9e40e00b9f311c8d2bfd5599b4c (patch) | |
| tree | 9792c5405808545d0c66951703bdcc1b641bb8f7 /lldb/packages/Python/lldbsuite/test | |
| parent | fe64323fd5c8137244fce75605f8de197eeea988 (diff) | |
| download | bcm5719-llvm-3b95986a32f1d9e40e00b9f311c8d2bfd5599b4c.tar.gz bcm5719-llvm-3b95986a32f1d9e40e00b9f311c8d2bfd5599b4c.zip | |
AMDGPU: Run AMDGPUCodeGenPrepare after scalar opts
The mul24 matching could interfere with SLSR and the other addressing
mode related passes. This probably is not the optimal placement, but
is an intermediate step. This should probably be moved after all the
generic IR passes, particularly LSR. Moving this after LSR seems to
help in some cases, and hurts others.
As-is in this patch, in idiv-licm, it saves 1-2 instructions inside
some of the loop bodies, but increases the number in others. Moving
this later helps these loops. In the new lsr tests in
mul24-pass-ordering, the intrinsic prevents introducing more
instructions in the loop preheader, so moving this later ends up
hurting them. This shouldn't be any worse than before the intrinsics
were introduced in r366094, and LSR should probably be smarter. I
think it's because it doesn't know the and inside the loop will be
folded away.
llvm-svn: 369991
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test')
0 files changed, 0 insertions, 0 deletions
