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authorDavid Green <david.green@arm.com>2019-04-21 09:54:29 +0000
committerDavid Green <david.green@arm.com>2019-04-21 09:54:29 +0000
commit0d741507f7ec1cb8925ed2c37408a1b0db079332 (patch)
tree145db7fababda9e25bb8e344e61716937aebbe0d /lldb/packages/Python/lldbsuite/test
parentdf02beb4165d3c07842878c6ed104622925be35b (diff)
downloadbcm5719-llvm-0d741507f7ec1cb8925ed2c37408a1b0db079332.tar.gz
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[ARM] Rewrite isLegalT2AddressImmediate
This does two main things, firstly adding some at least basic addressing modes for i64 types, and secondly treats floats and doubles sensibly when there is no fpu. The floating point change can help codesize in some cases, especially with D60294. Most backends seems to not consider the exact VT in isLegalAddressingMode, instead switching on type size. That is now what this does when the target does not have an fpu (as the float data will be loaded using LDR's). i64's currently use the address range of an LDRD (even though they may be legalised and loaded with an LDR). This is at least better than marking them all as illegal addressing modes. I have not attempted to do much with vectors yet. That will need changing once MVE is added. Differential Revision: https://reviews.llvm.org/D60677 llvm-svn: 358845
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