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authorSimon Tatham <simon.tatham@arm.com>2019-12-02 16:18:34 +0000
committerSimon Tatham <simon.tatham@arm.com>2019-12-02 16:20:30 +0000
commit01aefae4a173c32a0235feb9600beffbcd0308b4 (patch)
tree5c598fdc8af5b499f056a8e20a70a3febfeb3538 /lldb/packages/Python/lldbsuite/test
parenteffcdc3a82f2a32829170e7f7a2ff3d7853b612d (diff)
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[ARM,MVE] Add an InstCombine rule permitting VPNOT.
Summary: If a user writing C code using the ACLE MVE intrinsics generates a predicate and then complements it, then the resulting IR will use the `pred_v2i` IR intrinsic to turn some `<n x i1>` vector into a 16-bit integer; complement that integer; and convert back. This will generate machine code that moves the predicate out of the `P0` register, complements it in an integer GPR, and moves it back in again. This InstCombine rule replaces `i2v(~v2i(x))` with a direct complement of the original predicate vector, which we can already instruction- select as the VPNOT instruction which complements P0 in place. Reviewers: ostannard, MarkMurrayARM, dmgreen Reviewed By: dmgreen Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70484
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