summaryrefslogtreecommitdiffstats
path: root/lldb/packages/Python/lldbsuite/test/source-manager/TestSourceManager.py
diff options
context:
space:
mode:
authorSimon Pilgrim <llvm-dev@redking.me.uk>2020-01-14 11:41:26 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2020-01-14 11:41:47 +0000
commitfd42a4ac7a69adb92f87c7fa927509f177dcc6ca (patch)
tree261bcf0821c8072ac5c17e48c7908e09b0157519 /lldb/packages/Python/lldbsuite/test/source-manager/TestSourceManager.py
parenta43b0065c5c78eba3fb83881fb628f5b8182db64 (diff)
downloadbcm5719-llvm-fd42a4ac7a69adb92f87c7fa927509f177dcc6ca.tar.gz
bcm5719-llvm-fd42a4ac7a69adb92f87c7fa927509f177dcc6ca.zip
[X86][SSE] Add add(shl(and(x,c1),c2),c3) test case with non-uniform shift value
As mentioned by @nikic on rGef5debac4302, we should merge the guaranteed top zero bits from the shifted value and min shift amount code so they can both set the high bits to zero.
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/source-manager/TestSourceManager.py')
0 files changed, 0 insertions, 0 deletions
OpenPOWER on IntegriCloud