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| author | QingShan Zhang <48825004@qq.com> | 2019-10-30 07:56:35 +0000 |
|---|---|---|
| committer | QingShan Zhang <48825004@qq.com> | 2019-10-30 07:59:32 +0000 |
| commit | f15cf93899df3e8863207b40c3900facb0ccc356 (patch) | |
| tree | 2504e7989d4b4399807b82c533c56e3ce61e9ea3 /lldb/packages/Python/lldbsuite/test/sample_test/TestSampleTest.py | |
| parent | 264612e13833ef4018cd3b859b1ea2fe123a5d99 (diff) | |
| download | bcm5719-llvm-f15cf93899df3e8863207b40c3900facb0ccc356.tar.gz bcm5719-llvm-f15cf93899df3e8863207b40c3900facb0ccc356.zip | |
[PowerPC] Clear the sideeffect bit for those instructions that didn't have the match pattern
If the instruction have match pattern, llvm-tblgen will infer the sideeffect bit from the match pattern and it works well.
If not, the tblgen will set it as true that hurt the scheduling.
PowerPC has some instructions that didn't specify the match pattern(i.e. LXSD etc), which is manually selected post-ra according
to the register pressure. We need to clear the sideeffect flag for these instructions.
Differential Revision: https://reviews.llvm.org/D69232
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/sample_test/TestSampleTest.py')
0 files changed, 0 insertions, 0 deletions
