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| author | Roger Ferrer Ibanez <rofirrim@gmail.com> | 2019-04-11 15:13:12 +0000 |
|---|---|---|
| committer | Roger Ferrer Ibanez <rofirrim@gmail.com> | 2019-04-11 15:13:12 +0000 |
| commit | b621f041359b37828103a8ea1281e5c57169b3e2 (patch) | |
| tree | a5b19bf1f48aea8cf89eaeac94c7ea5ef2b80676 /lldb/packages/Python/lldbsuite/test/python_api | |
| parent | a41275a398399e1d3f3fda5bd423964fb5b28721 (diff) | |
| download | bcm5719-llvm-b621f041359b37828103a8ea1281e5c57169b3e2.tar.gz bcm5719-llvm-b621f041359b37828103a8ea1281e5c57169b3e2.zip | |
[RISCV] Diagnose invalid second input register operand when using %tprel_add
RISCVMCCodeEmitter::expandAddTPRel asserts that the second operand must be
x4/tp. As we are not currently checking this in the RISCVAsmParser, the assert
is easy to trigger due to wrong assembly input.
This patch does a late check of this constraint.
An alternative could be using a singleton register class for x4/tp similar to
the current one for sp. Unfortunately it does not result in a good diagnostic.
Because add is an overloaded mnemonic, if no matching is possible, the
diagnostic of the first failing alternative seems to be used as the diagnostic
itself. This means that this case the %tprel_add is diagnosed as an invalid
operand (because the real add instruction only has 3 operands).
Differential Revision: https://reviews.llvm.org/D60528
llvm-svn: 358183
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api')
0 files changed, 0 insertions, 0 deletions
